*SHA3 (KECCAK) :: Overview

Project maintainers


Name: sha3
Created: Nov 9, 2012
Updated: Dec 2, 2016
SVN Updated: Jan 29, 2013
SVN: Browse
Latest version: download
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Other project properties

Category: Crypto core
Language: Verilog
Development status: Stable
Additional info: Design done, FPGA proven, Specification done
WishBone Compliant: No
License: Others


SHA-3, originally known as Keccak [1], is a cryptographic hash function selected as the winner
of the NIST hash function competition [2]. Because of the successful attacks on MD5, SHA-0 and
theoretical attacks on SHA-1, NIST perceived a need for an alternative, dissimilar cryptographic
hash, which became SHA-3 [3].

NIST requires the candidate algorithms to support at least four different output lengths {224,256,384,512}
with associated security levels [4]. “SHA-3 512”, in which output length is 512-bit,
has the highest security level among all SHA-3 variants.

This project has implemented “SHA-3 512” hash function.

This project has implemented two cores, one (high-throughput) core designed to work in
high clock frequency (150 MHz) dedicated to ASIC or expensive FPGA (Virtex 6),
another (low-throughput) core designed to work in low clock frequency (100 MHz)
dedicated to cheap FPGA (Spartan 3). Because in many systems the clock frequency is
fixed for the entire chip, so even if the hash core can reach a high frequency it has to be
clocked at a lower frequency [5].

The code is FPGA-vendor independent, having been fully optimized, using only one
clock domain, not using any latch.

[1] Guido Bertoni, Joan Daemen, Michaël Peeters and Gilles Van Assche,
“The Keccak sponge function family: Specifications summary”,

[2] “NIST Selects Winner of Secure Hash Algorithm (SHA-3) Competition”,
NIST. Oct. 2012.

[3] “SHA-3”,
Wikipedia, the free encyclopedia,

[4] “Announcing request for candidate algorithm nominations for a new cryptographic hash algorithm (SHA-3) family”,
Federal Register Notices 72 (2007), no. 212, 62212–62220.

[5] Keccak implementation overview, version 3.2,

Synthesis result

The synthesis software is Xilinx ISE version 14.4.

The low throughput core has been synthesized targeting a very cheap Spartan 3 (XC3S5000-4FG900).

Number of Slices: 2,321
Number of Slice Flip Flops: 2,346
Number of 4 input LUTs: 4,499
Number of bonded IOBs: 552
Number of GCLKs: 1
Maximum Frequency: 117.3 MHz

The high throughput core has been synthesized targeting an expensive Virtex 6 (XC6VLX240T-1FF1156).

Number of Slice Registers: 2,220
Number of Slice LUTs: 9,895
Number of fully used LUT-FF pairs:1,673
Number of bonded IOBs: 585
Number of BUFG/BUFGCTRLs: 1
Maximum Frequency: 188.9 MHz


The low throughput core: 2.4 G bit / second if clock frequency is 100 MHz.

The high throughput core: 7.2 G bit / second if clock frequency is 150 MHz.


This project is licensed under the Apache License, version 2.

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