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Ultimate CRC :: Overview

Project maintainers

Details

Name: ultimate_crc
Created: May 5, 2005
Updated: Jan 14, 2016
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: ECC core
Language: VHDL
Development status: Stable
Additional info: ASIC proven, Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: GPL

Description

Ultimate CRC is a CRC generator/checker. Using generics the core can be fully customized. It creates a function of the data input and the CRC register using XOR-logic. Although the levels of logic gets very high for wide data inputs, the throughput still benefits from this architecture, as can be seen from the synthesis page.

Features

  • Executes in one clock cycle per data word
  • Any polynomial from 4 to 32 bits
  • Any data width from 1 to 256 bits
  • Any initialization value
  • Synchronous or asynchronous reset

Status

Revision 1.0 released.

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