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USB Host Core :: Overview

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Details

Name: usb_host_core
Created: Jul 12, 2015
Updated: Jul 26, 2015
SVN Updated: Jul 26, 2015
SVN: Browse
Latest version: download
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Other project properties

Category: Communication controller
Language: Verilog
Development status: Stable
Additional info: Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: GPL

Description

This IP core is a cutdown USB host controller which allows communications with full-speed (12mbps) USB devices.

The IP is accessed via a Wishbone slave interface (asynchronous read result) for control, status and data.

Data to be sent or received is stored in some internal FIFOs (which are configurable in size). The data is accessed through the Wishbone slave port. There is no DMA engine (e.g. a bus mastering interface) associated with this IP.

The core functions well, is very small, but is fairly inefficient in terms of CPU cycles required to perform USB transfers.
This core is not compliant with any standard USB host interface specification, e.g OHCI or EHCI.

Instantiation

Instance usbh and hookup to UTMI PHY interface and a Wishbone master (e.g. from your CPU).
The core requires a 48MHz clock input.

Testing

Verified under simulation and on FPGA with various USB devices attached (hubs, mass storage, network devices).

Configuration

TX_FIFO_DEPTH - Transmit FIFO size
TX_FIFO_ADDR_W - Transmit FIFO size (width of size field)
RX_FIFO_DEPTH - Receive FIFO size
RX_FIFO_ADDR_W - Receive FIFO size (width of size field)

Size

With the default configuration...

* the design contains 214 flops, 2 RAM cells (RX and TX FIFOs)
* synthesizes to more than the required 48MHz on a Xilinx Spartan 6 LX9 (speed -3)

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