Versatile FIFO :: Overview
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Details
Name: versatile_fifo
Created: Mar 31, 2009
Updated: Apr 1, 2009
SVN Updated: Mar 22, 2010
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Memory core
Language: Verilog
Development status: Beta
Additional info:
FPGA proven, Specification done
WishBone Compliant: No
License: LGPL
Introduction
The FIFO implementation outlined in this document can easily be configured to suit the following
- asynchronous FIFO with different clock domains for read and write sides
- synchronous FIFO with programmable flags
- multiple FIFO sharing the same memory resource
This FIFO can easily be extended to have common wishbone interface for all individual FIFO channels.