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Xilinx Configuration Port (ICAPE2) via Wishbone :: Overview

Project maintainers

Details

Name: wbicapetwo
Created: May 25, 2015
Updated: Jan 4, 2016
SVN Updated: Apr 22, 2016
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Other
Language: Verilog
Development status: Beta
Additional info: Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: GPL

Description

As the title says, this core provides access to the Xilinx Internal Configuration Access Port, Edition 2, via a 32-bit wishbone bus. The ICAPE2 contains address space for 32 registers, and this port provides access to all of them. Specific ports/registers that have been tested and proven include the warm boot start address (WBSTAR) and the command (CMD) register. Using these, together with the Quad SPI Flash core, I can reconfigure my Basys-3 development board from my bedroom nightstand without needing to come into the office and connect a JTAG cable or press the reset button. A very valuable capability therefore.

20160104 Update: The project now includes a file, wbicape6.v, which can be used to get access to the configuration port internal to a SPARTAN6 device. Testing has been sufficient to demonstrate that this port can read from the SPARTAN6 device. While the core should be able to write commands to the device as well, our test setup has not been sufficient to demonstrate capability there. Should you wish to help test this core on these devices, please contact me. Thanks!

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