Another Wishbone Controlled UART :: Overview

Project maintainers


Name: wbuart32
Created: Aug 25, 2016
Updated: Aug 28, 2016
SVN Updated: Jan 20, 2017
SVN: Browse
Latest version: download
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Other project properties

Category: Communication controller
Language: Verilog
Development status: Stable
Additional info: Design done, FPGA proven
WishBone Compliant: Yes
License: GPL


Forasmuch as many have taken in hand to set forth a UART core, ... It seemed good to me also, having had perfect (a good) understanding of all things from the very first, to write ... my own UART core.

One unique feature to this core is the ability of the Verilator test bench support code to forward the simulated UART connection over a TCP/IP link. This capability was first used in the Xula2-LX25 SoC core, has since been ported to the OpenArty project, and is now extracted from those projects here in the hopes that it may be useful to others projects and other individuals.

A second unique feature, and one that I find rather surprising, is the ease of configuring this core. I guess I thought every core would be so easy to configure. Not so. Unlike the UART-16550 core, this one is completely configured by setting just a single register. When using the sample Wishbone configuration, reading from the core is as simple as reading from a register, and sending out the UART is as simple as writing to a register. The core does not have an interrupt controller, yet still produces both transmit idle and receive ready interrupts.

The only real drawback to this core is that it doesn't include a FIFO. A second drawback is that it doesn't support hardware flow control. Both drawbacks are easy enough to rectify, I just ... haven't had any need to (yet). In all other respects, this is a very simple and easy to use controller.

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