Ethernet 10GE MAC :: Overview
Project maintainers
Details
Name: xge_mac
Created: May 19, 2008
Updated: Mar 20, 2012
SVN Updated: Feb 8, 2012
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Communication controller
Language: Verilog
Development status: Stable
Additional info:
Design done, FPGA proven, Specification done
WishBone Compliant: Yes
License: LGPL
Description
The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae.
Features
1. Interfaces
- XGMII Interface (64-bit single clock edge)
- POS-L3 like Interface for core logic side
- Wishbone Interface for control
2. Inter-Frame GAP
- Deficit Idle Count per Clause 46
3. Pause Frames
- Received Pause Frames filtering
- Receive Indication
4. LAN mode operation
5. Link Status
- Local Fault Detection
- Remote Fault Detection/Indication
6. Latency
- Low-latency flow-through mode (120ns TX, 160ns RX)
Release Notes
1. Some issues reported with synthesis of FIFO's in Xilinx. Recommend building FIFO's using Xilinx's core generator.
Status
- (05/31/08) Verilog code completed
- (06/06/08) SystemC and Verilog simulations completed
- (03/06/09) Validated in Altera FPGA running traffic against other MAC
- (03/06/09) Validated interfacing to external 10GE PHY using XAUI links
- (12/13/09) Changed packet interface to big endian
- (12/13/09) Added SERDES examples to tb_xge_mac.v
- (2/7/12) Updates for Xilinx synthesis
- (2/15/12) Core user reported passing traffic in Xilinx FPGA