OpenCores

Experimental Unstable CPU :: Overview

Project maintainers

Details

Name: xucpu
Created: Dec 31, 2014
Updated: Jan 25, 2015
SVN Updated: Jan 22, 2017
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: System on Chip
Language: VHDL
Development status: Alpha
Additional info: Design done, Specification done
WishBone Compliant: No
License: LGPL

Description

A simple 16-bit microprocessor together with a simple bus system. It utilises the Xilinx dual port ram features to be able to fetch instructions and use data memory at the same time. It is defined using RISC principles, featuring a small instruction set and overlapping execution. It is not completely pipelined. A first estimate gives a CPI of 2.2. Using a small memory a clock speed of 160 MHz is achievable on a Spartan-6 device with speed grade 2. Using larger memory will slow down the system due to net delays. The goal is to always release a simulator, an assembler and the core at the same time. The reason for this is that the instruction set will certainly change due to the development, implementation and measurement of the system software.

My own goals for this system are:

* Obtaining experience with building a microprocessor
* Have a target platform to develop a small Lisp system
* Have the possibility to develop and hook up IO devices without being bothered with a modern complex processor
* Offer a platform to other computer enthusiasts, comparable in complexity with the ZX Spectrum or the Commodore 64

Experimental refers to the fact that this SoC is used to experiment with VHDL, microprocessor, microprocessor architecture, and unstable to the fact that the instruction set will change in the future, based upon program measurements.

History

Why yet another microprocessor (system) core?

This project grew out of two interests, microprocessors and Lisp (both Common Lisp and Scheme).

I got interested in microprocessors in 1980, in Lisp around 2004. That was also the time I started experimenting with simulating microprocessors using software. A first design was completed from 2006 to 2007 when I simulated a self-designed 12-bit microprocessor at the signal level using the equivalent of MSI level components. Part of the design included a micro-program assembler and an assembler.

From 2008 to 2009 I was busy with implementing Scheme in Perl, learning from SICP. I started and stopped different projects for building microprocessors. From 2010 to 2012 I went back to school to get my master's degree in electronic engineering. Here I learnt VHDL. In this time I also acquired an Atlys board for doing my thesis. Around the same the company where I was, restructured, and I took the time to build another Lisp interpreter, but this time on top of a C engine. This provided me with some guiding lines on the kind of microprocessor I needed to build. This led to the definition of the ISA and the building of a simulator in Common Lisp. Hardware development started in July 2013.

The first VHDL simulation of the processor ran on Xilinx WebPack in October 2013. However, I was dissatisfied with the performance. I wanted to improve this by means of partial overlapping of instruction decoding and execution. The new implementation ran on 15 December 2014 and was mostly validated on 27 December. However, at that date a CALL and RET instruction were still missing, together with an interrupt scheme.

© copyright 1999-2017 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.