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XuLA2-LX25 SoC :: Overview

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Details

Name: xulalx25soc
Created: Dec 30, 2015
Updated: Jun 14, 2016
SVN Updated: Nov 11, 2016
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: System on Chip
Language: Verilog
Development status: Mature
Additional info: none
WishBone Compliant: Yes
License: GPL

Description

This project attempts to take two separate projects, the OpenCores ZipCPU and Xess.com's XuLA2-LX25, and merge them together into a single System on a Chip implementation. As currently implemented, this SoC offers the following peripherals to the ZipCPU within:

  • External Peripherals
    • 14 GPIO inputs, 15 GPIO outputs
    • PWM output
    • Rx and Tx UART ports
    • 1MB SPI Flash, together with a read/write controller
    • 32MB SDRAM capable of non-stop pipeline reads and writes
    • SD-Card, sharing the SPI wires of the flash
  • Internal Peripherals
  • Zip CPU Peripherals
    • 3x timers, each of which can be programmed either in a one shot mode or as a repeating interval timer
    • A watchdog timer, and a Wishbone bus watchdog timer
    • Two interrupt controllers
    • Direct Memory Access (DMA) Controller for unattended memory movement

Current Status

Although the project was only created in December, 2015, it is already fully featured. Most of the components have been pulled from other projects, either here on open cores or from within our personal vault. What remains is to complete the documentation describing the various components, to determine that these pieces can be built successfully from their SVN repository, and whether or not the peripheral list is sufficient for the project needs.

20160614: The SPI port based SD card now has a fully functional controller.

Unique Features

This System on a Chip controller has some unique features associated with it, above and beyond the peripherals listed above. Primary among those is the JTAG (or even UART) to 32-bit wishbone master conversion. This makes it possible for an external entity to read from or write to the wishbone bus. Uses include verifying whether or not peripherals work, as well as configuring the CPU, memory and flash for whatever purpose one might have. This particular capability was designed so that FPGA control programs can call a common set of bus interface functions to communicate with the FPGA, regardless of how the bus was actually implemented.

A second unique feature is a PWM driver that spreads its digital energy into higher (non-auditory) frequencies which can then be filtered out easier with a simple low-pass filter. As an example, sending a zero, or half pulse width, will result in alternating digital ones and zeros from the driver. While I expect this will have a pleasing effect on the ear, especially since these transitions will be outside of normal hearing range, this is the first time I have tried it and the jury's still out regarding whether or not it works or even works well.

Finally, while it may not really be that unique, this core does feature a fully functional SDRAM controller capable of one read cycle (or write cycle) every two clocks when pipelined. Unlike many other dynamic memory controllers, this one was not created from a proprietary, closed source, memory interface generation facility.

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