Zorro bus to Wishbone bridge :: Overview

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This project is in the early planning stage. I am collecting documentation for both busses and beginning to understand them, and refining the specifications. I'm collecting tools for design and test and preparing a development environment on my computer.

I intend to use as many freely available tools as possible, and will have some learning curve to be productive with them. I'm fairly familiar with simulating in Simvision, but I'd like to be doing this project with Icarus Verilog and GTKWave or Dinotrace instead, which I have never used before... I'm also interested in Verilator, but sounds like I'd need to learn SystemC for testbench stuff in that, and I'd also like to see things run in gplcver.

I've decided to make the RTL and any Makefiles, scripts, etc. in this project to be LGPL 2.1 or later. I'd pondered making documentation for this project under GFDL, but after discussions in various forums, I'm now planning for documentation (specs, test plans, etc) to be under LGPL 2.1 or later as well. While I'm told I can separate the two portions of this project into different licenses, it could forbid deriving any documentation from RTL etc. While I don't at the moment plan to derive docs from RTL or Makefiles, I might as well make it easy to do that if I change my mind, so the whole shebang will now be LGPL 2.1 or later.

I've started working on a specification document in OpenOffice. I'm hoping to do a decent document before I get lost in RTL coding and find myself hacking around more than should be, even as I don't expect this to be a hugely complex project. As some tools have been tricky to get running in Ubuntu Koala, I'm considering updating to Lynx. I have a small virtual machine for Lynx that seems to be doing better now, earlier had crashes and odd graphics at times. So either the virtual machine or Lynx or both seem to have been improved to work better together. Would be nice to have newer libs and tool versions already in the package system to reduce my self compilation of stuff so I have more time to work on projects and don't need to do as much computer and tool administration time.

Source Code

To check out the SVN trunk for this project:
[code]svn co http://opencores.org/ocsvn/zorro_to_wishbone_bridge/zorro_to_wishbone_bridge/trunk[/code]

In Eclipse, using Subversive Plugin:
URL = http://opencores.org/ocsvn/zorro_to_wishbone_bridge/zorro_to_wishbone_bridge
fill in your opencores.org login info
choose trunk or whatever to check out to your new project.

Description

This project intends to create a bridge between Wishbone and the Amiga Zorro II and Zorro III busses. As in the Amiga 3000/4000 computer families, it is intended to support both the Zorro II and Zorro III protocols at the same time on the same bus.

I am learning Verilog RTL for SoC/ASIC design and testbench simulation at work, and I think this will be an interesting "other than my day job" project to gain more experience with Verilog coding, tools, FPGA boards and FPGA tools. I also think that the Amiga in an FPGA community will benefit from gaining access to the numerous Wishbone peripheral cores here at opencores.org.

This project will be based on Zorro bus documentation as found in

1. the Commodore Amiga A3000T Service Manual
2. the Commodore-Amiga Inc. Zorro III Bus Specification rev 1.10
3. the Commodore Amiga A500/A2000 Technical Reference Manual
4. the Commodore-Amiga Inc. Amiga Hardware Reference Manual 3rd Edition
and other service manuals that seem relevant in my collection.

This project will be a Wishbone Rev.B4 bridge, which has just been released.

There are three possible uses for this bridge:

• as a Zorro slave peripheral card plugged into an Amiga motherboard Zorro slot
• as a Zorro bus master peripheral card plugged into an Amiga motherboard Zorro slot
• as a Zorro system controller on some motherboard which is in control of that motherboard's various Zorro slots (ie. it watches all busmaster acknowledge signals from all slots, sends busmaster grant signals to all slots, determines which acknowledge to send and when, etc. which are beyond a peripheral busmaster card's responsibilities) This is the mode which will be interesting to people wanting to add Zorro slots to the open-sourced MiniMig Amiga in an FPGA project as one example, as the system needs more control capabilities than a busmaster peripheral does. This is also the mode of interest if anyone wishes to create a replacement for Commodore's SuperBuster system bus controller chip.

I plan to implement this bridge in three phases, following the three usage modes as they seem to go in a nice order of complexity and build on previous modes:

Phase 1:	Implement Zorro II / Zorro III slave peripheral mode to Wishbone master bus. This allows connecting a Wishbone slave peripheral to a Zorro host system. (Zorro slaves may be able to DMA into the host system under direction from the host system driver software, but will not be able to request control of the bus)
Phase 2:	Implement Zorro II / Zorro III busmaster peripheral mode to Wishbone slave bus. This allows connecting a Wishbone master bus/peripheral to a Zorro slave. This should allow two uses: Wishbone master peripheral on a Zorro busmastering peripheral plugin card, inserted into a Zorro host system. Wishbone host system can use one, possibly multiple Zorro slave peripheral plugin cards, but no Zorro busmastering peripheral plugin cards. (busmaster capable Zorro cards should work fine as slaves, and may be able to DMA into the host system under direction from the host system driver software, but will not be able to request control of the bus due to lack of Zorro bus arbitration logic)
Phase 3:	Implement Zorro II / Zorro III system bus controller mode, which adds in Zorro bus arbitration logic. This will allow a Wishbone host system full use of all Zorro slave and busmaster peripheral plugin cards to request control of the bus and DMA into the host system.

Testing of this core will utilize an Avnet Xilinx® Spartan®-3 Evaluation Kit, which is a PCI card format eval/development system including a Xilinx Spartan 3 XC3S1500 FPGA device.

1. A small adapter board will allow the 100pin Zorro edge connector to fit onto this FPGA board's PCI edge connector when testing slave and busmaster peripheral modes in an Amiga 3000 desktop and/or A4000T computer. Host Amiga computer will use a SuperBuster rev 11 system bus controller chip to control its Zorro bus.
2. Another adapter board will be made to provide a connection to an Amiga 4000 desktop computer's Zorro backplane daughterboard, possibly also the Amiga 3000 desktop computer's equivalent if supporting both is reasonable. This easily provides for a number of Zorro slots while reducing PCB board design on my part. Testing in this mode will likely include porting the MiniMig, DragonBall/68K Wishbone interface, and ao68000 or ae68 cores to this evaluation board. This combination should give me a Wishbone Minimig core attached to a Wishbone CPU, everything in verilog, where the traditionally Minimig-paired TG68 is a VHDL non-Wishbone CPU. A single HDL language should make life easier on me, as will existing Wishbone CPU and interface to Minimig's 68000 bus.