CBU Graduation Project
Project maintainers
Details
Name: cbu_v1
Created: Feb 7, 2024
Updated: Apr 22, 2024
SVN: No files checked in
Bugs: 0 reported / 0 solved
Created: Feb 7, 2024
Updated: Apr 22, 2024
SVN: No files checked in
Bugs: 0 reported / 0 solved
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Other project properties
Category:Processor
Language:Verilog
Development status:Mature
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Mature
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
https://github.com/SelahattinAbakay/graduation-project
The link contains that architecture of verilog Based Processor Design Project.
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