Written in: Any language VHDL Verilog & VHDL Verilog SystemC Bluespec C/C++ Other Stage: Any stage planning mature alpha beta stable License: Any license GPL LGPL BSD Others Wishbone version: Any version B.3 B.4
ASIC proven Design done FPGA proven Specification done OpenCores Certified

marked with

Arithmetic core

Prototype board

Communication controller

Coprocessor

Crypto core

DSP core

ECC core

Library

Memory core

Other

Processor

System on Chip

System on Module

System controller

Testing / Verification

Video controller