Skordal, Kristian

Potato Processor

Hi Skordal,

From RISCV specification, we have to create a new register in IRF logic.
"There is one additional user-visible register: the program counter pc holds the address of the current instruction."

--
Regards,
Santhosh Kumar.

inclusion of PC register in IRF

Hi Skordal,

I have a doubt on misalignment logic. 

Why we have to check the LSB bits of alu resultant data ?
How we can explore the data misalignment cause happened ?

After exception cause what about PC value and how it will come out ?

If PC increment with 1 value, data and instruction misalignment will happen ?

Doubt on misalignment ?

Hi Skordal,

I have been going through the RISC V ISA and saw that there are different LOAD and STORE instructions based on the size of the data like LW,LB. while looking into potato I saw that the core checks the last 2 bits of the output of the alu to identify for data misalignment and then generates an appropriate exception corresponding to data width misalignment. My doubt is a check of the last 2 bit to 2'b00 can also be a valid data.

as per the below snippet

case mem_size is
	when MEMOP_SIZE_HALFWORD =>
	   if alu_result(0) /= '0' then
		data_misaligned <= '1';
	   else
	        data_misaligned <= '0';
	   end if;
	when MEMOP_SIZE_WORD =>
	   if alu_result(1 downto 0) /= b"00" then
		data_misaligned <= '1';
	   else
		data_misaligned <= '0';
	   end if;
	when others =>
	        data_misaligned <= '0';
end case;

Also what is the rationale behind instruction misalignment check.

doubt in memory load ans store type data sizes

Hi Skordal,

We are working on potato processor. Generated the imem and empty HEX files and copied into ISE directory.
While simulate the design we are getting the Errors like 

FATAL_ERROR:Simulator:CompilerAssert.h:40:1.67 - Internal Compiler Error in file ../src/VhdlExpr.cpp at line 5355

a WebCase with this project attached at http://www.xilinx.com/support.
FATAL_ERROR:Simulator:CompilerAssert.h:40:1.67 - Internal Compiler Error in file ../src/VhdlExpr.cpp at line 5355

Thank you,

--
Regards,
Santhosh Kumar

About on Simulation !!

hello Skordal,

I have a quite basic doubt regarding the implementation of the privilege modes in RISC V ISA. The RISC V ISA has 4 modes viz. Machine, hypervisor, supervisor and User. Among these I plan to just work with Machine, Supervisor and User mode.
Looking at the RISC V privilege ISA v1.7 it seems that the CSR address space is divided between the CSR from the 4 modes. So assuming Hypervisor is not to be implemented, how to implement the other 3 modes viz. machine,supervisor and user mode.
Can I have 3 physical register sets belonging to the Machine, Supervisor and User mode each or I just need to have a Machine mode CSR implemnted in RTL and then need to add Supervisor and User mode registers.

Iam not able to figure out how to do this implementation in RTL. It will b really great if you could give me some idea about this.

Thanks a lot!!

doubt in privilege mode implementation

Hi Skordal,

I would like to know if FENCE and FENCE.I is supported by potato and a brief description of how it works from a logical implementation perspective. I searched online but i`am not able to get much info on this or if you could suggest some resources that I could go through.


Tussen Takk !!

About on FENCE and FENCE.I

Hi Skordal,

Thanks for the last updates that you gave, have been very useful. However, I got one small doubt though. The potato processor is based on RV32I basically a RISC V ISA, so if I want to run a C code to add 2 numbers and then run it on potato how can I achieve this. Can i use the riscv-gcc and then use the generated elf to get the imem_hex and dmem_hex or is there any other way to do this..

Thanks !!

Akshay

doubt in running C tests

Hello Kristian,

I have been looking at the potato processor and have some doubts. I simulated the core in xilinx (ISE 14.1) ISE`s isim simulator with an imem_add.hex and a dmem_add.hex file as part of the testbench. The simulation works perfect. 

Next, I try with a subtraction logic by writing down a simple c code and compiling it with the riscv-gcc and get a elf file. Using the extract_hex.sh script I generate the imem_hex and dmem_hex for the subtraction C code.

However, when I include these files in the testbench, the simulation still performs addition operation. I was able to identify this by pulling out the input and output signals at the alu_instance that shows the operands x and y as well as the result.

Can you suggest if there is anything that I have been doing wrong or i need to do some more steps.

Thanks a lot!!

doubt in different test usage

Hi Team,

Can you provide the documentation of Potato Processor.
is this, Sodor 5-satge riscv processor ?

--
Regards,
Santhosh K

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Potato Processor