Rev |
Log message |
Author |
Age |
Path |
211 |
Add custom printf function to reduce program memory footprint (the TI/RH GCC version is huge). Note that this function was created by DJ Delorie ( http://www.delorie.com/ ) |
olivier.girard |
3127d 11h |
/openmsp430/trunk/core/sim/ |
207 |
Simulation now works seamlessly under Linux, OS-X and Windows (Cygwin) |
olivier.girard |
3155d 01h |
/openmsp430/trunk/core/sim/ |
204 |
Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). |
olivier.girard |
3259d 01h |
/openmsp430/trunk/core/sim/ |
202 |
Add DMA interface support + LINT cleanup |
olivier.girard |
3266d 01h |
/openmsp430/trunk/core/sim/ |
200 |
Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. |
olivier.girard |
3427d 00h |
/openmsp430/trunk/core/sim/ |
192 |
Number of supported IRQs is now configurable to 14 (default), 30 or 62. |
olivier.girard |
3827d 02h |
/openmsp430/trunk/core/sim/ |
186 |
Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 |
olivier.girard |
4080d 02h |
/openmsp430/trunk/core/sim/ |
180 |
Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-) |
olivier.girard |
4122d 00h |
/openmsp430/trunk/core/sim/ |
178 |
Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-) |
olivier.girard |
4131d 00h |
/openmsp430/trunk/core/sim/ |
175 |
Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint bug with CALL instructions.
- modified data read watchpoint behavior to also trigger with read/modify/write instructions.
- removed unused ports. |
olivier.girard |
4148d 00h |
/openmsp430/trunk/core/sim/ |
154 |
The serial debug interface now supports the I2C protocol (in addition to the UART) |
olivier.girard |
4255d 01h |
/openmsp430/trunk/core/sim/ |
151 |
Add possibility to configure custom Program, Data and Peripheral memory sizes. |
olivier.girard |
4339d 23h |
/openmsp430/trunk/core/sim/ |
149 |
Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface) |
olivier.girard |
4343d 01h |
/openmsp430/trunk/core/sim/ |
145 |
Add Dhrystone and CoreMark benchmarks to the simulation environment. |
olivier.girard |
4393d 01h |
/openmsp430/trunk/core/sim/ |
142 |
Beautify the linker script examples. |
olivier.girard |
4414d 01h |
/openmsp430/trunk/core/sim/ |
141 |
Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) |
olivier.girard |
4418d 00h |
/openmsp430/trunk/core/sim/ |
138 |
Update simulation scripts to support Cygwin out of the box for Windows users. |
olivier.girard |
4430d 11h |
/openmsp430/trunk/core/sim/ |
134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4462d 01h |
/openmsp430/trunk/core/sim/ |
128 |
Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) |
olivier.girard |
4559d 01h |
/openmsp430/trunk/core/sim/ |
122 |
Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator. |
olivier.girard |
4631d 01h |
/openmsp430/trunk/core/sim/ |
115 |
Add linker script example. |
olivier.girard |
4760d 02h |
/openmsp430/trunk/core/sim/ |
111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4769d 01h |
/openmsp430/trunk/core/sim/ |
106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4825d 00h |
/openmsp430/trunk/core/sim/ |
105 |
Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way. |
olivier.girard |
4840d 01h |
/openmsp430/trunk/core/sim/ |
103 |
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL. |
olivier.girard |
4845d 07h |
/openmsp430/trunk/core/sim/ |
102 |
Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:
- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+ |
olivier.girard |
4846d 00h |
/openmsp430/trunk/core/sim/ |
101 |
Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. |
olivier.girard |
4846d 02h |
/openmsp430/trunk/core/sim/ |
99 |
Small fix for CVER simulator support. |
olivier.girard |
4850d 01h |
/openmsp430/trunk/core/sim/ |
98 |
Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated. |
olivier.girard |
4850d 01h |
/openmsp430/trunk/core/sim/ |
95 |
Update some test patterns for the additional simulator supports. |
olivier.girard |
4854d 01h |
/openmsp430/trunk/core/sim/ |