Lightweight 8080 compatible core :: Overview
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Name: light8080
Created: Oct 25, 2007
Updated: Jun 26, 2011
SVN Updated: Feb 9, 2011
SVN: Browse
Latest version: download
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Other project properties
Category: Processor
Language: VHDL
Development status: Alpha
Additional info:
FPGA proven
WishBone Compliant: No
License: GPL
Description
This is a simple, small microprogrammed Intel 8080 CPU binary compatible core.
There are already at least two other 8080-compatible cores in Opencores, both of them well proven. This one is different because it emphasizes area instead of cycle-count compatibility or speed.
I have tried to minimize logic size and complexity as much as possible, at the expense of speed. At about the same size as a Picoblaze on a Spartan 3 (204 LUTs + 1 BRAM), this is perhaps amongst the smallest 8-bit CPU cores available. On the other hand, it is rather slow in clock frequency and particularly in cycles per instruction (25 to 50% more clocks per instruction than the original, which is an awful lot! -- see the design notes). Besides, the 2 KBytes of dedicated fpga ram it does use may in some designs be more valuable than a large number of logic blocks.
The source is quite simple: a single file with some 1300 lines of straightforward, moderately commented VHDL code; plus a microcode source file from which the microcode table embedded into the vhdl was assembled. However, the simplicity may be deceptive; it can be argued that the complexity of the system has been moved from the RTL to the microcode...
A description of the circuit and its microcode is included in the design notes and the respective source files. The microcode assembler (a perl script) is included too, though it is not necessary if you just want to use the core and not modify it.
This is just a fun project I created to learn vhdl; my design goal was to get the simplest possible 8080-compatible core, at the smallest possible size, at any reasonable speed. And above all, at a minimum cost in development time -- so I could get something worthy done in the very limited time available.
Though I think I accomplished my goal, the resulting core is probably of little practical use: it is certainly no match for a picoblaze in its application niche, and it is not small enough to compensate for its lack of features (the smallest Nios II is only 2 or 3 times larger). And there are better 8080 cores around, as I said.
I am in debt with Scott A. Moore for his cpu8080 core. Though I have not used his code in this project, I studied it and did use much of the research and test material that he made available at this site.
Features
- Microcoded design, very simple circuit.
- Microcode source and assembler included, though the vhdl microcode table can be edited directly.
- Slower than original in clocks per instructions (about 25 to 50%, comparative table included in the design notes).
- 100% binary compatible to original 8080.
- Synchronized to positive clock edges only.
- Signal interface very simplified. Not all original status info available (no M1, for instance).
- Synchronous memory and i/o interface, with NO WAIT STATE ability.
- INTA procedure similar to original 8080, except it can use any instruction as int vector.
- Undefined/unused opcodes are NOPs.
Performance (standalone CPU, synthesis only):
Xilinx XST on Spartan 3 (-5 grade):
200 LUTs plus 1 BRAM @ 80 MHz (optimized for area)
228 LUTs plus 1 BRAM @ 100 MHz (optimized for speed)
618 LUTs @ 53 MHz (optimized for area, no block ram)
Altera Quartus on Cyclone 2:
369 LEs plus 4 M4Ks @ 67 MHz (balanced optimization)
Status
The core has already executed some quite large pieces of original code in hardware, including the Microsoft Altair 4K Basic and some parts of CP/M. Interrupt response has been simulated and tested in real hardware.
Yet, that does not guarantee that there aren't any bugs left. The core is essentially finished but the project will remain in 'alpha' state until it passes an exhaustive functional test bench and/or it boots CP/M.
Altair 4K Basic Demo
Altair Basic is an early implementation of Basic (1975) for the 8080-based Altair computer. I have included in the project a demo running the unmodified binaries on the light8080 core. See instructions and status log below.Assuming you are using Quartus-2 and targetting a Terasic DE-1 dev board (for which the demo is tailored), you need to follow these steps:
- Create a new project for the DE-1 board, (device EP2C20F484C7, etc.).
- Add all the vhdl files in /vhdl/demo, plus the main cpu file light8080.vhdl, to your project.
- Select file c2sb_4kbasic_cpu.vhdl as 'top' entity.
- Configure dual-purpose pin nCEO as regular i/o (Device settings->Device and pin options->Dual-purpose pins)
- Import the pin location constraints from file /vhdl/demo/c2sb_4kbasic.csv
- Ready to go. Synthesize and program. It is advisable to have a terminal connected before loading the FPGA (19200/8/N/1).
Make sure you're using the last revision; some earlier revisions had a bug in the csv pin constraints file that misplaced the clock input.
Note that resetting the CPU does not reload the program (the program is stored in an initialized 4K RAM which is all the CPU can see). Once the program has started, the only way to cleanly restart it is reprogramming the FPGA. This is why the terminal should be connected before programming.
I admit this is a nasty hack but it saves me the need to build a bootloader. For this quick-and-dirty demo this limitation is acceptable.
Right after startup the program will ask you a few configuration questions. See the picture below for a sample session. Remember the 4K Basic only uses caps letters and is a bit unforgiving by today's standards.
Here's a snapshot of a sample session on my terminal emulator (putty):
The fact that the floating point routines do work makes me think that the core works as an original 8080 and few bugs remain, if any. While not very useful in practice, the 4K Basic demo is a good confidence builder.
Here's a link to the Altair Basic manual.
Update, 7-10-2010:
I have put together a little Altair 4K Basic Demo, ready to run on a Cyclone-2 DE-1 board (pin declaration file included).
All you need to do is hook a terminal to the board (19200/8-N-1) and you'll be able to run a minimalistic Basic with floating point support. The Altair Basic documentation is not included but is widely available.
The demo includes only 4K bytes of internal FPGA RAM (initialized with the 4K basic code) and a serial port. It is not an emulation of the whole Altair, nor would it be a good starting point for one: all the demo files other than the CPU core are very rough and the resulting RTL is not as efficient as it might be.
But at least the Basic demo makes a good confidence-builder: I am now almost certain no bugs remain in the core :) Of course I can't be sure until I do a proper test bench, and thus the core remains in 'unfinished' state.
Since the demo only uses internal FPGA resources, an external clock input and a serial interface, it should be easily portable to other development boards. All the demo logic is clocked at 50MHz; if you change this you'll need to edit some parameters in the serial port source files too.
I have noticed that the microcode ALU operation encoding table in the documentation is wrong; the real values are those shown in the perl script. I plan to fix it as soon as I have a long enough stretch of spare time.
Update, 7-10-2010:
Bug fix: The XOR instructions were not updating the flags properly; I only caught this error while setting up the 4K basic demo, it slipped undetected by the main test bench and a lot of original code I've been running. The fix has increased the LUT count by 3 or 4 so the figures quoted above are no longer fully valid.
Update, 7-23-2009:
Interrupt response has been fixed, and the interrupt simulation test bench updated accordingly. The interrupt line has already been tested in hardware (used for single-stepping CP/M code).
Update, 8-18-2008:
A microcode bug has been found in INR M that the test bench (and other code I've been running on it) did not catch. I've just checked in a corrected version (Thanks to Tomasz Olszewski for the accurate bug report!). See the bug report in the tracker for the details. The project needs a much stronger test bench before upgrading to beta status.
Summary (8-28-2008):
The core has executed a functional test and some original code in hardware. Exhaustive tests, execution of large original software and interrupt response demo in hardware still to be done.
The core has passed a functional test, the 'Kelly Smith test', both in simulation and in hardware. Though the Kelly test is by no means exhaustive, I am now pretty confident that the design is sound and no big errors are going to show up (I do expect to find microcode bugs yet).
The Kelly Smith test is a 8080 CPU test created in 1980 which tests for most flags, modes and instructions (excludes i/o, interrupt response and does not test all postconditions of all instructions). Though it is not an exhaustive test, it is quite complete and has been an invaluable help in the development.
I have used the Kelly test version found in http://opencores.org/project,cpu8080 (Scott Moore's cpu8080 core site), slightly modified to fit my hardware set up. Besides, I have built a small simulation-only test bench (vhdl/test/light8080_tb0.vhdl) which includes the Kelly tests and can be used as a regression test of sorts.
The core has executed the kelly tests test code on two hardware incarnations: a Spartan 3 and a Cyclone 2, both at 50MHz (sources similar to simulation test bench, not included). In both cases they worked at first trial without glitches or funny behaviours. Yet, there was at least one hidden bug which I only detected after running the scs-1 monitor (a microcode bug).
I have been tinkering with the core a bit and there seems to be nothing wrong with it. Therefore I think I can put the project in 'alpha' status.