OpenCores: Mission

Gateware

This website is a community portal for professionals, amateurs, and enthusiasts interested in the field of digital design engineering. The site gives users open access to view, download, reuse, and share gateware designs. OpenCores specializes on bundles of structured files forming self-confined units, most commonly known as Intellectual Properties (IP) “cores”, coded in Hardware Description Language (HDL).

These therefore fall into the category classified as “gateware”: a layer in the electronics development chain positioned in between “hardware”, i.e. a PCB (Printed Circuit Board) or a packaged chip; and “firmware”: most commonly used to describe a set of decoded and executed instructions for a microprocessor.

It also provides or promotes all the associated technology that revolves around such IP cores.

The need

There are two categories of devices which are running gateware digital designs, hence making use of IP cores: FPGAs (Field Programmable Gate Arrays) and ASICs (Application Specific Integrated Circuits).

Since the end of the nineties, Deep SubMicron (DSM) designs began to include many millions of gates in a single ASIC (Application Specific Integrated Circuits). Since then, the number of gates continues to constantly grow each new generation, with the result that the design time gets increasingly longer and the technology complex to manage. This can result in inadequate time-to-market and excessive costs.

The same applies to Field Programmable Gate Arrays (FPGA) where the device complexity shifted from a circuit a designer could draw on a piece of paper to something one single designer won’t be able to fulfil and handle within a reasonable amount of man-hours.

The technical solution to the problem of managing the scaling of technology, the increasing complexity, and broadening multi-men design processes related to FPGAs and ASICs is rather obvious: reuse cores as much as possible, and share the demanding workload of streamlining, documentation, and extensive verification.

Historically, cores available for integration are proprietary and must be purchased from established vendors, often at very high prices. These costs can be burdensome, especially for small design teams with limited funding. High-priced entry barriers pose a problem for research and education institutions as well. Proprietary cores are hard to integrate due to the multiplicity of incompatible design and test tools. Last but not least, vendor lock-in might present obstacles for components obsolescence and long term support, an aspect of crucial importance for projects with long life- cycles.

Main objective

Our main objective is to promote collective design and publication of gateware projects under license schemes suitably modelled for such Intellectual Properties (IP) Cores. We are committed to the ideal of publicly available, openly usable and re-usable, Free and Open Source gateware. Through our community portal we try to inspire, promote, and foster third parties to follow the example and do the same.

Subsidiary objectives

We have set the following subsidiary objectives as the means of reaching our main objective:

• Develop Open Source IP Cores, gateware and related platforms
• Develop standards for Open Source IP Cores, gateware and related platforms
• Create tools and methods for Open Source IP Cores, gateware and platforms development
• Provide consistent, easy to access, documentation for all the above

These tools and methods should allow unbound vast dissemination of knowledge; and foster the exchange of information among international teams to develop gateware for hardware platforms in an open and collaborative way.

Expected benefits

We truly believe that Open Source gateware is the solution to most of the problems associated with proprietary cores. The following advantages and benefits has been clearly identified:

• Each core will have a larger user base, which will ensure peer review, better support, extensive documentation, appropriate and logical structuring, including better implementation examples to work from.
• The complete source code is available – which consists of HDL files, basic constraints, and project management scripts - so any developer can easily find what is need to know about the core, how to use it, and how to modify it, if required.
• There is no charge for accessing and using all the OpenCores IP (Intellectual Property) gateware Cores.
• Eventually, as cores and standards for them are developed, cores will become more standards-compliant than proprietary cores.