New feature: code metrics user ranking
posted by OpenCores, Admin on 2017-12-08

Two new features deployed today: (i) a starring system of the cores, (ii) a better overview on the number of bugs reported and solved per core.

OC-site: mail server down [solved]
posted by OpenCores, Admin on 2017-10-06

OpenCores email aliases restored

OC-site mail server down
posted by OpenCores, Admin on 2017-10-01

OpenCores email aliases currently unavailable

OpenCores breaking news: new ownership
posted by OpenCores, Admin on 2017-09-22

Oliscience: took over the development and maintenance of the community portal

OC-site scheduled maintenance [done]
posted by OpenCores, Admin on 2017-09-03

OpenCores portal undergone important maintenance

OC-site scheduled maintenance | Sat 02 and Sun 03 September
posted by OpenCores, Admin on 2017-09-01

OpenCores portal undergoing important maintenance

OC-site overload disruptions [solved]
posted by OpenCores, Admin on 2017-08-26

Mail server overloaded

OC-forums down for unscheduled maintenance [solved]
posted by OpenCores, Admin on 2017-07-11

The problem is now solved.

Best,
/:/ OC-team

OC-forums down for unscheduled maintenance
posted by OpenCores, Admin on 2017-07-11

OC-site: the forums are temporarily down due unscheduled maintenance.

EnSilica develops sureCore’s new, Ultra-Low Power IoT reference platform
posted by Humbugpr on 2017-06-05

EnSilica and sureCore have announced that EnSilica has developed sureCore’s new, ultra-low power IoT reference platform targeted principally at the development of the next generation of wearable consumer and medical applications.

EnSilica opens specialist Design Center for RF and low power sensing applications
posted by Humbugpr on 2016-10-25

EnSilica has further expanded its network of specialist design centers with the establishment of a new facility near Oxford (UK) focusing on RF and low power sensing applications. The new facility is headed by Alan Wong, formerly IC Design Director at Frontier Microsystems, and it extends EnSilica's skills-base addressing the needs of wireless connected IoT and wearable products.

EnSilica teams with BaySand to provide ASIC UltraShuttle-65 multi-project wafer customers with configurable IP solutions
posted by Humbugpr on 2016-08-17

EnSilica to provide BaySand’s customers with configurable eSi-RISC processor cores, eSi-Connect processor peripherals, eSi-Crypto encryption and eSi-Comms communications IP solutions as well hardware accelerators

EnSilica and Micrium partner to port µC/OS-III RTOS to eSi-RISC processor cores
posted by Humbugpr on 2016-06-06

EnSilica and Micrium have partnered to successfully port Micrium’s µC/OS-III® RTOS to EnSilica’s family of eSi-RISC processor cores. Micrium’s µC/OS-III is available on eSi-RISC with immediate effect.

EnSilica launches eSi-ECDSA cryptographic IP for standards-compliant automotive Car2x communications
posted by Humbugpr on 2016-05-09

EnSilica has launched the eSi-ECDSA cryptographic IP designed to help meet the high security communication and latency requirements of automotive Car2Car and Car2Infrastructure (Car2x) applications that form part of today’s emerging Intelligent Transport Systems.

is the openMSP430 on its way to SPACE ?
posted by Olivier, Girard on 2014-12-31

is the openMSP430 on its way to SPACE ?

First open-source Hybrid Memory Cube controller released
posted by Juri, Schmidt on 2014-09-30

openHMC - an open-source Hybrid Memory Cube Controller

ZTEX releases new Artix 7 FPGA Board with USB and DDR3 SDRAM
posted by Stefan, Ziegenbalg on 2014-04-10

ZTEX releases USB-FPGA Modules 2.13 with Artix 7 XC7A35T to XC7A100T FPGA, USB 2.0 controller, 256 MByte DDR3 SDRAM and on-board voltage regulators.

ZTEX releases a FPGA Board with largest Artix 7 FPGA
posted by Stefan, Ziegenbalg on 2013-11-25

ZTEX releases USB-FPGA Module 2.16 with Artix 7 XC7A200T FPGA, USB 2.0 Controller, on-board voltage regulators and many I/O's.

A 2-D IDCT Architecture without Memory Registers For Multiple Video Standards
posted by swami, nathab on 2013-02-04

Abstract — A IDCT architecture is designed for

multistandard inverse transform. The proposed

architecture is used in multistandard decoder

of MPEG-2, MPEG-4 ASP, H.264/AVC and

VC-1. Two circuits share strategies, factor

share (FS) and adder share (AS), are applied

to the inverse transform architecture for saving

its circuit resource. Finally, the architecture is

extended as 2-D using registers as row to column

decomposition

Keywords — Circuit share, high-definition

video, multistandard inverse transform, multi-

standard, IDCT, reconfigurable architecture

open hardware survey
posted by Andres, Cicuttin on 2012-05-21

This is an invitation to participate to a survey on an open hardware initiative for sciintific purposes in line with UNESCO mission. The results will be share with all participants and will be used to raise awarnes of new ways of open collaboration and project sustainability in line with opencores' spirit.
Many thanks,
Andres Cicuttin,
Technical Assistant
ICTP (UNESCO-IAEA)