Opensource FPGA Protocol Engines for Real-Time Control Networks

Abstract: The Paper examines the prospect of using an opesource approach for developing and maintaining opensource FPGA Protocol Engines for Real-Time Control Networks. The success of opensource operating systems & software for PCs is a strong indicator that such an approach lowers costs, enhances flexibility and makes technologies more accessible. However due to the different nature of Protocol Engines from that of Operating systems a one-to-one comparison cannot be drawn but due to lower silicon costs and improvement in FPGA design techniques such an approach seems to be a viable option. 1.Introduction The Protocol Engine forms the backbone of any Control Network. One of the most widely used control network protocols is the Controller Area Network Protocol [1] or simply known as CAN. The CAN Protocol was developed by Bosch. It is widely used in the Automotive Industry for implementing passive safety systems. Another such protocol is Byteflight [2], which was developed by BMW. BMW has used the Byteflight systems in its production vehicles. CAN and Byteflight can be considered to be 1st generation control networks due to their non-deterministic nature. For active safety systems and future by-wire applications 2nd Generation control networks need to be deterministic in nature. The on-going development of these protocols has highlighted one major obstacle that is standardization of these protocols and proprietary issues. The sections of the paper that follow will examine the reliability and feasibility of developing opensource FPGA protocol engines without ignoring commercial aspects of technologies. 2. FPGA – The ‘Magic’ Chip The range of functions that an FPGA can perform with true parallelism makes it truly a magic chip. The FPGA market is dominated by two names: - Xilinx - Altera Consistent with the trends seen in cost vs. performance of other silicon devices, FPGAs too have come a long way since their inception by Xilinx [3] back in 1984. FPGAs once were only used for glue logic but today’s FPGAs offer much more and can be used as ASIC replacements. 3. FPGA Design Flow Hardware Design/Description Languages are the best choice for FPGA designs and IP development. Once the RTL coding is done and tested in hardware it can also be moved to an ASIC platform. The following diagram (Figure 1) gives a good picture of the design flow for FPGA design. FIGURE 1: FPGA Design Flow 4. Control Net Backbone- The Protocol Engine The protocol engine forms the backbone of the network and for future by-wire applications this will have to be time-triggered and fault-tolerant. The following diagram (Figure 2) shows a generic bus-type control network. FIGURE 2: Generic Bus-Type Control Network The development of the protocol engine, starting form specification to fabrication, is a time consuming and lengthy process that requires in depth fault analysis and formal verification. This work is in progress for 2nd generation networks. However all such work for 1st generation networks is complete and tested silicon is available off the shelf. Their specifications have also been made available in the public domain. Of the 1st generation networks the most widely used is the CAN protocol. Bosch owns most of the patents of CAN. Although there are no restrictions on developing an opensource CAN IP but for any commercial use the protocol license from Bosch is an indispensable prerequisite. 5. The Opensource Phenomena The software industry is perhaps the best indicator that using opensource as a business model as well as a platform for rapid development is a winning formula. The success of opensource operating systems for PCs speaks for itself. The same approach can also be used for hardware IP cores that are essentially software descriptions/designs of hardware. Although there is a mark difference between the development and maintenance of common PC software and hardware cores written in HDL but due to lower silicon costs and the availability of freely available synthesis and implementation tools, the opensource approach to hardware cores has become possible. One example of such a venture is the Opencores [4]. Opencores is a web-based repository, which has brought together many hardware developers and is perhaps a pioneer in opensource hardware core development. 6. FPGA Protocol Engine – The Opensource Way In view of the discussion so far using Opensource as means for developing FPGA protocol controllers seems like a good option that would have a positive outcome. Therefore the authors made an endeavour to develop an opensource CAN core. For this purpose first and foremost concern was that of copyrights. Therefore Bosch was contacted and the reply from Bosch stated that there are no restrictions on developing an opensource CAN IP but for any commercial use the protocol license from Bosch is required. The results of this endeavour look promising the core was initially developed in Verilog and later translated in VHDL. Following (Listing 1) is synthesis report of the CAN core using Xilinx WebPack and keeping the target a Spartan-II XC2S100 FPGA. Design Summary -------------- Number of errors: 0 Number of warnings: 0 Number of Slices: 1,065 out of 1,200 88% Number of Slices containing unrelated logic: 0 out of 1,065 0% Number of Slice Flip Flops: 564 out of 2,400 23% Total Number 4 input LUTs: 1,542 out of 2,400 64% Number used as LUTs: 1,395 Number used as a route-thru: 51 Number used for Dual Port RAMs: 96 (Two LUTs used per Dual Port RAM) Number of bonded IOBs: 32 out of 140 22% IOB Flip Flops: 1 Number of GCLKs: 2 out of 4 50% Number of GCLKIOBs: 2 out of 4 50% Total equivalent gate count for design: 20,261 Additional JTAG gate count for IOBs: 1,632 LISTING 1: FPGA Utilisation Report The WebPack synthesis and implementation software from Xilinx, which is freely downloadable from the Internet, comes with a variety of tools that make it a good quality tool with no price tag attached, ideal for opensource development. Altera [5] also offers a similar software package called Quartus Web Edition. A quite useful tool that comes with the WepPack is for viewing the FPGA after the Place & Route to give an idea of how the FPGA recourses have been utilized. Figure 3 shows a portion of the post place & route view of the CAN core. FIGURE 3: Post Place & Route View 7. Conclusion The prospect of using opensource as a platform for developing FPGA Protocol engines for Real-Time control networks looks promising. The flexibility that a soft core gives a designer will enable more complex and stable systems to evolve with time. The Automotive sector along with other sectors like aerospace and automation can all benefit from the contribution of thousands of IP developers worldwide without. A particular area for opensource protocol engine development could be 2nd generation control networks for Automotive applications. One of the biggest obstacles in bringing forth by-wire technologies to automotives is higher development cost along with safety and standardization issues. Using the opensource platform the cost overhead can be reduced substantially and control nets will continues to evolve faster to become more and more stable. Special Acknowledgement to Mr Igor Mohor for making the CAN core available. References [1] www.can.bosch.com [2] www.byteflight.com [3] www.xilinx.com [4] www.opencores.org [5] www.altera.com