Demonstration of Asynchronous Design on FPGA
by sotiriou on 2004-09-27
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Asynchronous design is simple and can be done easily on FPGA designs. A demonstrator of an asynchronous version of the DLX processor has been shown at several conferences this year.
The demonstrator design was developed by the Asynchronous Circuits and Systems Group of ICS-FORTH and of the University of Crete, and by the Microelectronics Group of Politecnico di Torino.
It consists of a simple embedded system, implemented on a Digilent D2E FPGA board, centered around ASPIDA DLX Processor, an asynchronous open-source version of the DLX RISC CPU.
Processor, memory and a VGA driver are implemented on a Xilinx Spartan IIE device using the ISE tools from Xilinx.
The whole system, including the asynchronous CPU and its interfaces to memories and legacy synchronous components, such as the VGA driver, was implemented on a standard FPGA device using standard design tools.
To see the demo please visit
http://www.ics.forth.gr/carv/async/demo/
To download the DLX core/demo visit
ftp://139.91.184.6/pub/ASPIDA/
The demonstrator design was developed by the Asynchronous Circuits and Systems Group of ICS-FORTH and of the University of Crete, and by the Microelectronics Group of Politecnico di Torino.
It consists of a simple embedded system, implemented on a Digilent D2E FPGA board, centered around ASPIDA DLX Processor, an asynchronous open-source version of the DLX RISC CPU.
Processor, memory and a VGA driver are implemented on a Xilinx Spartan IIE device using the ISE tools from Xilinx.
The whole system, including the asynchronous CPU and its interfaces to memories and legacy synchronous components, such as the VGA driver, was implemented on a standard FPGA device using standard design tools.
To see the demo please visit
http://www.ics.forth.gr/carv/async/demo/
To download the DLX core/demo visit
ftp://139.91.184.6/pub/ASPIDA/