Proposed project on DFM- CAD through Lihtography simulation
by texasjohn on 2006-02-17
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source:
I would like to propose a project. Being new to this forum I wanted to check and see if people felt it was appropriate and worthwhile.
Our company deals with the lithography simulation of final tape out. Therefore the back end of Design. There is a real dilema associated with GDSII or OASIS databases being available for basic research, demonstration, benchmarking or transfer between groups. Some of the basic problems that are occuring are:
1) Inaccurate modeling of the actual result on wafer
2) Transfer of the models back into design so that electrical analysis can be made of actual product performance versus design layout.
3) Statistical analysis and verification of timing, power, etc based off of projected variations due to manufacturing.
There are also other issues and variations occuring that definately have impact at sub-100 nm or even larger. For example, leff is impacted by the slope of the gate (shadowing by implant). Transfer of gate slope after final etch is copied from the resist profile.
Thus instead of the idea of sharing code in an "opensource" format as VHDL or verilog I propose the sharing of tapeout related databases.
We would be willing to contribute by actually using our software to verify the "on-wafer" results. We would check for litho hotspots and "litho-friendly" designs. We ask in return that the database be true open source so that we can collaborate openly in the design community.
I appreciate your time in reviewing this article and would welcome your opinions.
Best regards,
Texasjohn
Our company deals with the lithography simulation of final tape out. Therefore the back end of Design. There is a real dilema associated with GDSII or OASIS databases being available for basic research, demonstration, benchmarking or transfer between groups. Some of the basic problems that are occuring are:
1) Inaccurate modeling of the actual result on wafer
2) Transfer of the models back into design so that electrical analysis can be made of actual product performance versus design layout.
3) Statistical analysis and verification of timing, power, etc based off of projected variations due to manufacturing.
There are also other issues and variations occuring that definately have impact at sub-100 nm or even larger. For example, leff is impacted by the slope of the gate (shadowing by implant). Transfer of gate slope after final etch is copied from the resist profile.
Thus instead of the idea of sharing code in an "opensource" format as VHDL or verilog I propose the sharing of tapeout related databases.
We would be willing to contribute by actually using our software to verify the "on-wafer" results. We would check for litho hotspots and "litho-friendly" designs. We ask in return that the database be true open source so that we can collaborate openly in the design community.
I appreciate your time in reviewing this article and would welcome your opinions.
Best regards,
Texasjohn