VHDL DESIGN STANDARDS
by arroxo2 on 2013-03-22
source: http://communities.mentor.com/mgcx/docs/DOC-3513
source: http://communities.mentor.com/mgcx/docs/DOC-3513
This technical report is the first draft based on the author experience along years developing FPGA designs and RTCA DO-254 HW certification, various information found in articles, VHDL guidelines and on the internet.
It has been prepared with support from seminars, courses and feedback from the principal manufacturers support.
This document can also been seen as a set of guidelines to FPGA design for safety applications (avionics, railway, automotive, space, etc…). It provides a development method which outlines a development flow that is commonly considered as sufficient for FPGA design. The document also provides hints that should be considered by any FPGA designer. Emphasis has also been placed on Single Event Upset (SEU) hardships.
The purpose of these methods is to ensure a high quality of the developed VHDL models, so they can be efficiently used and maintained with a low effort throughout the full life-cycle of the modelled hardware.
(http://communities.mentor.com >> search:"DO254")
It has been prepared with support from seminars, courses and feedback from the principal manufacturers support.
This document can also been seen as a set of guidelines to FPGA design for safety applications (avionics, railway, automotive, space, etc…). It provides a development method which outlines a development flow that is commonly considered as sufficient for FPGA design. The document also provides hints that should be considered by any FPGA designer. Emphasis has also been placed on Single Event Upset (SEU) hardships.
The purpose of these methods is to ensure a high quality of the developed VHDL models, so they can be efficiently used and maintained with a low effort throughout the full life-cycle of the modelled hardware.
(http://communities.mentor.com >> search:"DO254")