VHDL Coding Standards for DO254

by arroxo2 on 2014-12-05
This technical report is the first draft based on the author experience along years developing FPGA designs and RTCA DO-254 HW certification, various information found in articles, VHDL guidelines and on the internet.
It has been prepared with support from seminars, courses and feedback from the principal manufacturers support.
This document can also been seen as a set of guidelines to FPGA design for safety applications. The document also provides hints that should be considered by any FPGA designer. Emphasis has also been placed on Single Event Upset (SEU) hardships.
The purpose of these methods is to ensure a high quality of the developed VHDL models, so they can be efficiently used and maintained with a low effort throughout the full life-cycle of the modelled hardware.

This guide does not represent an official position for the FAA, EASA or RTCA / Eurocae related committees. It should be discussed with the appropriate certification authority when considering for actual projects.
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