OpenRISC 1000
SMT/superscalar #6
Closed ocghost opened this issue over 19 years ago
ocghost commented over 19 years ago
Nice to se others having the same ideas (although alot earlier) about multithreading via register windows, but how about the idea of making it superscalar but not focusing on parellelism in threads but rather between several. This means having multiple IF frontends with a single issuing unit, thus having the apperance of an SMP system. I belive this is called Simultanious Multi Threading, or HyperThreading in Intel marketspeak.
Now if only I had the time... /Anders
ocghost commented over 18 years ago
I agree. What about a speculative Tomasulo architecture?
Luca
jeremybennett commented almost 13 years ago
<p>
Transferred to OpenRISC bugzilla (<a href="http://bugzilla.opencores.org/show_bug.cgi?id=50">Bug 50</a>).
</p>
<p>
Marking closed in this bugtracker.
</p>
marcus.erlandsson was assigned almost 13 years ago
jeremybennett closed this almost 13 years ago
© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.