OpenRISC 1000
In the Wishbone specification one can read that during a burst the wb_sel signal must be kept constant.
One can obtain an error during such bursts if the dcqmem_ci_i signal wents high during the burst. The dcqmem_ci_i is in this case configured to correspond to the most significant bit in the address output from the cpu (dcpu_adr_cpu).
DMMU and IMMU is disabled.
The address from the cpu is erroneous in this case, and is produced in the LSU, where the LSU executes a LSUOP_NOP, and therefore signextends the ex_insn 16-bit immediate field.
If bit ex_insn15 is a one, one can possibly get an error, since then dcqmem_ci_i = dcpu_adr_cpu31 = ex_insn15.
The problem is that we observe a case where dcqmem_ci_i wents high during only one clockcycle during a cache refill burst, and therefore the wb_sel signal goes down for one clockcycle. Which in our case led to sampling old data, because of a too early ack signal.
I'm working on this.
We have seen this as well but didn't really have time to debug it properly. However, in an old version of or1200_dc_top.v we used the following assignment for the dcsb_sel_o:
assign dcsb_sel_o = (dc_en & (dcfsm_burst | (dcfsm_biu_read & !dcfsm_biu_write & !dcdmmu_ci_i))) ? 4'b1111 : dcpu_sel_i;
That is, we made sure that the dcsb_sel_o would always output 4'b1111 while bursting. We are not sure if this is the correct fix for it however but a simple testcase where the bug was present was fixed in this case.
My fix is not correct since dcfsm_burst seems to go high for one clock cycle while fetching a region where the cache should be inhibited.
Hi all.
It might be a similar bug. When effectively caching it, and when prefetch-internal-aborted too. I corrected it as follows.and the bus cycle is good. but Is this really correct? Anyone can evalated this problem? changed file or1200_iwb_biu.v or1200_wb_biu.v or1200_dc_fsm.v or1200_dc_top.v or1200_ic_fsm.v or1200_ic_top.v
1.problem in BIU? (or1200_iwb_biu.v or1200_wb_biu.v)
2.problem in Cache FSM? (or1200_dc_fsm.v, or1200_dc_top.v, or1200_ic_fsm.v, or1200_ic_top.v)
1.problem in BIU? (or1200_iwb_biu.v or1200_wb_biu.v)
<pre> ----or1200_iwb_biu.v //Added ~repeated_access_ack `ifdef OR1200_NO_BURSTS //wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry & ~repeated_access | aborted & ~wb_ack_i; wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry & ~repeated_access & ~repeated_access_ack | aborted & ~wb_ack_i; `else //wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry & ~repeated_access | biu_cab_i | aborted & ~wb_ack_i; wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry & ~repeated_access & ~repeated_access_ack | biu_cab_i | aborted & ~wb_ack_i; `endif //wb_stb_o <= #1 (biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~retry & ~repeated_access | aborted & ~wb_ack_i; wb_stb_o <= #1 (biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~retry & ~repeated_access & ~repeated_access_ack | aborted & ~wb_ack_i; //Select aborted // wb_sel_o <= #1 biu_sel_i; wb_sel_o <= #1 (aborted) ? wb_sel_o: biu_sel_i; // wb_cab_o <= #1 biu_cab_i; wb_cab_o <= #1 (aborted) ? wb_cab_o: biu_cab_i; ----or1200_wb_biu.v //Select aborted // wb_sel_o <= #1 biu_sel_i; wb_sel_o <= #1 (aborted) ? wb_sel_o: biu_sel_i; // wb_cab_o <= #1 biu_cab_i; wb_cab_o <= #1 (aborted) ? wb_cab_o: biu_cab_i; </pre>2.problem in Cache FSM ?(or1200_dc_fsm.v,or1200_dc_top.v,or1200_ic_fsm.v,or1200_ic_top.v)
<pre> ----or1200_dc_fsm.v //assign burst = ..... & !cache_inhibit assign burst = ..... & !cache_inhibit & !dcqmem_ci_i </pre>can not post....why?..this is test.
2.problem in Cache FSM? (or1200_dc_fsm.v,or1200_dc_top.v,or1200_ic_fsm.v,or1200_ic_top.v)
<pre> ----or1200_dc_fsm.v //assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss & !cache_inhibit assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss & !cache_inhibit & !dcqmem_ci_i ----or1200_dc_top.v //assign dcsb_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcqmem_ci_i) ? ___1111 : dcqmem_sel_i; assign dcsb_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & dcfsm_burst) ? ___1111 : dcqmem_sel_i; ----or1200_ic_fsm.v //assign burst = (state == `OR1200_ICFSM_CFETCH) & tagcomp_miss & !cache_inhibit assign burst = (state == `OR1200_ICFSM_CFETCH) & tagcomp_miss & !cache_inhibit & !icqmem_ci_i ----or1200_ic_top.v //assign icbiu_sel_o = (ic_en & icfsm_biu_read) ? ___1111 : icqmem_sel_i; assign icbiu_sel_o = (ic_en & icfsm_biu_read & icfsm_burst) ? ___1111 : icqmem_sel_i; </pre>done :) The cause is quote(4_b1111).
Fixed this in the OpenRISC v3.