On Wednesday 28 January 2004 10:49 am, Bill Cox wrote:

[large snip]





A while back I offered up Confluence to the OpenCores community for
this very concept: flexible IP and web-based netlist generation. The
offer still stands.

On a similar note, a Confluence user recently ported OR1200 to the
language. (Ken, are you going to post ORCF anytime soon?)

Bill, it's a great idea. If there's anything I can do to assist, let
me know.

Regards,
Tom

Tom Hawkins wrote:


Hi, Tom.

I am very impressed with confluence. You've done something pretty
cool there. My main strike against it is that it's not
open-source. Of course, the other choices all seem to have
draw-backs. Perlilog is Verilog-centric, and I recently found out
just how much the VHDL users around here insist backing their
language. JavaHDL requires the user to install the JVM. My old
OpenLPM project is still buggy, and not as cool as Confluence, but
it could probably be offered as open-source.

I'm not against charging for software, and I think you deserve to
make money on Confluence. However, I feel an SoC Builder will get
more interest if it's an open-source front-to-back.

I agree. It would be ideal if OpenCores only depended on open-source
software. But the truth is every OC project requires commercial EDA.
(If I'm wrong, please show me the open-source path from RTL to GDSII.
;-))

> -- Users post pre-synthesized cores to OpenCores (as well as RTL
> source), in a generic netlist format (this is something I know how to do).
> -- We write open-source tools that can combine those cores
> automatically, taking core-specific options, and running the author's
> customization scripts.
> -- This tool then spits out gate level Verilog/VHDL to the desired
> target (Xilinx, Altera, LSI, etc).
>
> The impact on design productivity is potentially huge.
>
> Any interest in discussing the idea?
>
> Bill

Aloha!
...

For some inspiration I recommend looking at the SOPC builder by Altera. It is in
effect a Perl based tool that allows you to select cores. Connect them using the
Avalon fabris, set addresses, interrupts etc. Each core has it's own tab (i.e. a
specified customization ability that the SOPC frameork just needs to be able to
launch.

After setting all features needed for the given SoPC-design, you press Generate
and it will produce a system with corresponding RTL, SW-interface, memory map
etc. Vey neat. I belive you could download a trial version of SOPC-builder fromn
Alteras webpage. It's IMHO definetly worth a testrun.

And there is no magic trick behind this either. It's base configuration files
for the Avalon fabric, address maps and symbol lists. The Perl scrips copies and
modiies the files as needed. We (InformAsic) have a similar setup for our own
internal SoC-platform. Not as fancy with GUI etc, but still it generates the
complete SoC for us in very short time.

There is another benefit with these systems: You lower the risk of changing
parts that shouldn't be changed. When adding cores to a system you just add
THOSE files and configurations, the rest of the system is automatically included
and "off limits" from mistakes that tend to happen when done manually.