Hi Mark, Are you willing to share the wrapper? I can add it to the tarball. More people are asking for this ... Thanks, Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of Mark McDougall Sent: Friday, January 27, 2006 12:21 AM To: Discussion list about free open source IP cores Subject: Re: [oc] I2C ip core integration for ALTERA FPGAs froger.e0300617 at etud.univ-ubs.fr wrote: I recently sucessfully integrated the I2C core onto an Avalon bus in a Cyclone II without any problems whatsoever. I used a top-level wrapper to convert the unsigned wb_adr_i to std_logic_vector and also remove the std_logic generic ARST_LVL (SOPC Builder barfs on std_logic parameters). I guess the only difference here is that I'm not actually talking to it from the NIOS, but rather from another micro which interfaces to the Avalon bus externally. But I can confirm that it does indeed work. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266 _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Did you connect clock and data signals correctly? It is a bit tricky because you don't use the clock and data out lines for the actual data transfer. They are always 0. You have to use the data and output enable to make 1 and 0. Hope it is of help. Regands, David ----- Original Message ----- From: froger.e0300617 at etud.univ-ubs.frfroger.e0300617 at e...> To: Date: Tue Jan 24 20:24:08 CET 2006 Subject: [oc] I2C ip core integration for ALTERA FPGAs

Hello, I have created the avalon bus as Guido told in this post. I wanted to know if he used the wrapper to convert the address bus from unisgned to standard logic vector.....or not? If yes, I have no idea of how to do it....any suggestions? After created the avalon bus, have I to use the oc_i2c_master.h function to write and read the I2C? thanks, Giuseppe -- View this message in context: http://www.nabble.com/Re%3A-I2C-ip-core-integration-for-ALTERA-FPGAs-t995020.html#a3086749 Sent from the OpenCores - IP Cores forum at Nabble.com.

Hello, I have created the avalon bus as Guido told in this post. I wanted to know if he used the wrapper to convert the address bus from unisgned to standard logic vector.....or not? If yes, I have no idea of how to do it....any suggestions? After created the avalon bus, have I to use the oc_i2c_master.h function to write and read the I2C? thanks, Giuseppe -- View this message in context: http://www.nabble.com/Re%3A-I2C-ip-core-integration-for-ALTERA-FPGAs-t995020.html#a3086749 Sent from the OpenCores - IP Cores forum at Nabble.com.

ferrarino wrote:
I tried to compile the project but without the wrapper there is an error: a mismatching between the wb_adr_i of the sopc (std_logic_vector) and the I2C_master_top (unsigned). So I need this wrapper.......how do I create it? thanks, Giuseppe -- View this message in context: http://www.nabble.com/Re%3A-I2C-ip-core-integration-for-ALTERA-FPGAs-t995020.html#a3088654 Sent from the OpenCores - IP Cores forum at Nabble.com.

Hello, I have created the avalon bus as Guido told in this post. I tried to compile the project but there is an error: a mismatching between the wb_adr_i of the sopc (std_logic_vector) and the I2C_master_top (unsigned). So I need this wrapper.......how do I create it? Please tell me any suggestions!!!! After created the avalon bus, have I to use the oc_i2c_master.h function to write and read the I2C? thanks, Giuseppe -- View this message in context: http://www.nabble.com/Re%3A-I2C-ip-core-integration-for-ALTERA-FPGAs-t995020.html#a3088698 Sent from the OpenCores - IP Cores forum at Nabble.com.

Hello, I have created the avalon bus as Guido told in this post. I tried to compile the project but there is an error: a mismatching between the wb_adr_i of the sopc (std_logic_vector) and the I2C_master_top (unsigned). So I need this wrapper.......how do I create it? Please tell me any suggestions!!!! After created the avalon bus, have I to use the oc_i2c_master.h function to write and read the I2C? thanks, Giuseppe -- View this message in context: http://www.nabble.com/Re%3A-I2C-ip-core-integration-for-ALTERA-FPGAs-t995020.html#a3088698 Sent from the OpenCores - IP Cores forum at Nabble.com.

I have been able to to the wrapper and link it to the avalon bus of NiosII. Now I have the common problem that I'm not able to write in the registers except prescalere one. What have I to do? P.s. the scl and sda line are pulled up with 4,7k resistors.(even if now I have done a weak pull-up directly on pins by Quartus) Any suggestions? Thanks, Giuseppe -- View this message in context: http://www.nabble.com/Re%3A-I2C-ip-core-integration-for-ALTERA-FPGAs-t995020.html#a3142083 Sent from the OpenCores - IP Cores forum at Nabble.com.