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Parallel Array Processor Project by Unknown on Sep 28, 2004			Not available!
Aloha! On EE Times is running an article series about new technology that engineers as a collective consider to be interesting. Of these there are a couple that should relate pretty well to the things you are looking at for your parallel array processor project: MathStar - building coarse grained FPGA like chips where the LUTs are replaced by something similar to a FSM with routing channels: <A HREF="http://www.mathstar.com/">http://www.mathstar.com/</A> <A HREF="http://www.eeproductcenter.com/pld-fpga/review/showArticle.jhtml?articleID=21401410">http://www.eeproductcenter.com/pld-fpga/review/showArticle.jhtml?articleID=21401410</A> IPFlex a Japanese company that builds a dynamically reconfigurable processor: <A HREF="http://www.ipflex.com/en/index.html">http://www.ipflex.com/en/index.html</A> <A HREF="http://www.eeproductcenter.com/pld-fpga/review/showArticle.jhtml?articleID=18902448">http://www.eeproductcenter.com/pld-fpga/review/showArticle.jhtml?articleID=18902448</A> Anyone played with these? -- Med vÃ¤nlig hÃ¤lsning, Yours Joachim StrÃ¶mbergson - Alltid i harmonisk svÃ¤ngning. VP, Research & Development ---------------------------------------------------------------------- InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÃ–TEBORG / Sweden Tel: +46 31 68 54 90 Fax: +46 31 68 54 91 Mobile: +46 733 75 97 02 E-mail: <A HREF="http://www.opencores.org/mailman/listinfo/cores">joachim.strombergson at informasic.com</A> Home: www.informasic.com ---------------------------------------------------------------------- Aloha! On EE Times is running an article series about new technology that engineers as a collective consider to be interesting. Of these there are a couple that should relate pretty well to the things you are looking at for your parallel array processor project: MathStar - building coarse grained FPGA like chips where the LUTs are replaced by something similar to a FSM with routing channels: http://www.mathstar.com/ http://www.eeproductcenter.com/pld-fpga/review/showArticle.jhtml?articleID=21401410 IPFlex a Japanese company that builds a dynamically reconfigurable processor: http://www.ipflex.com/en/index.html http://www.eeproductcenter.com/pld-fpga/review/showArticle.jhtml?articleID=18902448 Anyone played with these? -- Med vÃ¤nlig hÃ¤lsning, Yours Joachim StrÃ¶mbergson - Alltid i harmonisk svÃ¤ngning. VP, Research & Development ---------------------------------------------------------------------- InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÃ–TEBORG / Sweden Tel: +46 31 68 54 90 Fax: +46 31 68 54 91 Mobile: +46 733 75 97 02 E-mail: joachim.strombergson at informasic.com Home: www.informasic.com ----------------------------------------------------------------------

Parallel Array Processor Project by nico on Sep 28, 2004			nico Posts: 21 Joined: Jun 21, 2008 Last seen: May 11, 2009
[q] Aloha! On EE Times is running an article series about new technology that engineers as a collective consider to be interesting. Of these there are a couple that should relate pretty well to the things you are looking at for your parallel array processor project: MathStar - building coarse grained FPGA like chips where the LUTs are replaced by something similar to a FSM with routing channels: <A HREF="http://www.mathstar.com/">http://www.mathstar.com/</A> <A HREF="http://www.eeproductcenter.com/pld-fpga/review/showArticle.jhtml?articleID=21401410">http://www.eeproductcenter.com/pld-fpga/review/showArticle.jhtml?articleID=21401410</A> [/q] its funny to see that's look so much like what we speak about. [q] IPFlex a Japanese company that builds a dynamically reconfigurable processor: <A HREF="http://www.ipflex.com/en/index.html">http://www.ipflex.com/en/index.html</A> <A HREF="http://www.eeproductcenter.com/pld-fpga/review/showArticle.jhtml?articleID=18902448">http://www.eeproductcenter.com/pld-fpga/review/showArticle.jhtml?articleID=18902448</A> [/q] This one is like the previous plus a cpu onboard. It run at almost 10 time slower... the price will make the difference. mathstar product seems to be cheaper than FPGA. It should be nice to play with ! [q] Anyone played with these? -- Med vÃ¤nlig hÃ¤lsning, Yours Joachim StrÃ¶mbergson - Alltid i harmonisk svÃ¤ngning. VP, Research & Development ---------------------------------------------------------------------- InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÃ–TEBORG / Sweden Tel: +46 31 68 54 90 Fax: +46 31 68 54 91 Mobile: +46 733 75 97 02 E-mail: <A HREF="http://www.opencores.org/mailman/listinfo/cores">joachim.strombergson at informasic.com</A> Home: www.informasic.com ---------------------------------------------------------------------- _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] Aloha! On EE Times is running an article series about new technology that engineers as a collective consider to be interesting. Of these there are a couple that should relate pretty well to the things you are looking at for your parallel array processor project: MathStar - building coarse grained FPGA like chips where the LUTs are replaced by something similar to a FSM with routing channels: http://www.mathstar.com/ http://www.eeproductcenter.com/pld-fpga/review/showArticle.jhtml?articleID=21401410 its funny to see that's look so much like what we speak about. IPFlex a Japanese company that builds a dynamically reconfigurable processor: http://www.ipflex.com/en/index.html http://www.eeproductcenter.com/pld-fpga/review/showArticle.jhtml?articleID=18902448 This one is like the previous plus a cpu onboard. It run at almost 10 time slower... the price will make the difference. mathstar product seems to be cheaper than FPGA. It should be nice to play with ! Anyone played with these? -- Med vÃ¤nlig hÃ¤lsning, Yours Joachim StrÃ¶mbergson - Alltid i harmonisk svÃ¤ngning. VP, Research & Development ---------------------------------------------------------------------- InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÃ–TEBORG / Sweden Tel: +46 31 68 54 90 Fax: +46 31 68 54 91 Mobile: +46 733 75 97 02 E-mail: joachim.strombergson at informasic.com Home: www.informasic.com ---------------------------------------------------------------------- _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Parallel Array Processor Project by Unknown on Sep 28, 2004			Not available!
On Tue, 28 Sep 2004 <A HREF="http://www.opencores.org/mailman/listinfo/cores">nico at seul.org</A> wrote: [q]> MathStar - building coarse grained FPGA like chips where the LUTs are > replaced > by something similar to a FSM with routing channels: > > <A HREF="http://www.mathstar.com/">http://www.mathstar.com/</A> > <A HREF="http://www.eeproductcenter.com/pld-fpga/review/showArticle.jhtml?articleID=21401410">http://www.eeproductcenter.com/pld-fpga/review/showArticle.jhtml?articleID=21401410</A> >[/q] its funny to see that's look so much like what we speak about.[/q] I don't get it. How is this different from SIMD machines like the old CM-1 or Masspar systems (apart from the fact that it's a single chip)? I mean, what makes mathstar like FPGAs rather than processors? Graham On Tue, 28 Sep 2004 nico at seul.org wrote: > MathStar - building coarse grained FPGA like chips where the LUTs are > replaced > by something similar to a FSM with routing channels: > > http://www.mathstar.com/ > http://www.eeproductcenter.com/pld-fpga/review/showArticle.jhtml?articleID=21401410 > its funny to see that's look so much like what we speak about. I don't get it. How is this different from SIMD machines like the old CM-1 or Masspar systems (apart from the fact that it's a single chip)? I mean, what makes mathstar like FPGAs rather than processors? Graham

Parallel Array Processor Project by nico on Sep 28, 2004			nico Posts: 21 Joined: Jun 21, 2008 Last seen: May 11, 2009
[q] On Tue, 28 Sep 2004 <A HREF="http://www.opencores.org/mailman/listinfo/cores">nico at seul.org</A> wrote: [q]> MathStar - building coarse grained FPGA like chips where the LUTs are > replaced > by something similar to a FSM with routing channels: > > <A HREF="http://www.mathstar.com/">http://www.mathstar.com/</A> > <A HREF="http://www.eeproductcenter.com/pld-fpga/review/showArticle.jhtml?articleID=21401410">http://www.eeproductcenter.com/pld-fpga/review/showArticle.jhtml?articleID=21401410</A> >[/q] its funny to see that's look so much like what we speak about.[/q] I don't get it. How is this different from SIMD machines like the old CM-1 or Masspar systems (apart from the fact that it's a single chip)? I mean, what makes mathstar like FPGAs rather than processors? [/q] more routing ressources, more way to configure it independantly, IMHO. nicO [q] Graham _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] On Tue, 28 Sep 2004 nico at seul.org wrote: > MathStar - building coarse grained FPGA like chips where the LUTs are > replaced > by something similar to a FSM with routing channels: > > http://www.mathstar.com/ > http://www.eeproductcenter.com/pld-fpga/review/showArticle.jhtml?articleID=21401410 > its funny to see that's look so much like what we speak about. I don't get it. How is this different from SIMD machines like the old CM-1 or Masspar systems (apart from the fact that it's a single chip)? I mean, what makes mathstar like FPGAs rather than processors? more routing ressources, more way to configure it independantly, IMHO. nicO Graham _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Parallel Array Processor Project by Unknown on Jan 25, 2006			Not available!
hi iam searching for code or project that imoplements instruction in parallel ie., parallel procssor tht implements instructions in parallel in verilog using xilinx. so plz if have ,can u post it to me. thanks sowmya hi iam searching for code or project that imoplements instruction in parallel ie., parallel procssor tht implements instructions in parallel in verilog using xilinx. so plz if have ,can u post it to me. thanks sowmya

Parallel Array Processor Project by markus on Feb 3, 2006			markus Posts: 32 Joined: Dec 9, 2002 Last seen: Apr 30, 2013
[q] hi iam searching for code or project that imoplements instruction in parallel ie., parallel procssor tht implements instructions in parallel in verilog using xilinx. so plz if have ,can u post it to me. thanks sowmya [/q] Did you found the thread I started some time ago? At least the subject is exactly the same... My project (about cellular processing arrays) is going on, altought slowly, and realworld implementations might see the daylight at this century :-) Anyway, I'm doing my finally started Master Thesis about the issue. hi iam searching for code or project that imoplements instruction in parallel ie., parallel procssor tht implements instructions in parallel in verilog using xilinx. so plz if have ,can u post it to me. thanks sowmya Did you found the thread I started some time ago? At least the subject is exactly the same... My project (about cellular processing arrays) is going on, altought slowly, and realworld implementations might see the daylight at this century :-) Anyway, I'm doing my finally started Master Thesis about the issue.

Parallel Array Processor Project by Unknown on Feb 9, 2006			Not available!
Could you show me this processor calculate posibility and architecture? Processor's Architecture and FPGA development is my hobby :) Regands, Denis -----Original Message----- From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores-bounces at opencores.org</A> [mailto:<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores-bounces at opencores.org</A>] On Behalf Of <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores-request at opencores.org</A> Sent: Thursday, February 09, 2006 4:46 AM To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A> Subject: Cores Digest, Vol 27, Issue 2 Send Cores mailing list submissions to <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A> To subscribe or unsubscribe via the World Wide Web, visit <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> or, via email, send a message with subject or body 'help' to <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores-request at opencores.org</A> You can reach the person managing the list at <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores-owner at opencores.org</A> When replying, please edit your Subject line so it is more specific than "Re: Contents of Cores digest..." Today's Topics: 1. 1024 point FFT processor (<A HREF="http://www.opencores.org/mailman/listinfo/cores">p_bharatin at yahoo.com</A>) 2. ata-3 IP-core (<A HREF="http://www.opencores.org/mailman/listinfo/cores">jverhoeve at gmail.com</A>) 3. RE: ata-3 IP-core (Richard Herveille) 4. Re: I2C ip core integration for ALTERA FPGAs (<A HREF="http://www.opencores.org/mailman/listinfo/cores">David.Wessels at gmail.com</A>) 5. Re: ata-3 IP-core (Mark McDougall) 6. Re: Parallel Array Processor Project (<A HREF="http://www.opencores.org/mailman/listinfo/cores">markus at reaaliaika.net</A>) 7. hardware implementation of JVM...urgent!!!! (<A HREF="http://www.opencores.org/mailman/listinfo/cores">shikhanshu at gmail.com</A>) 8. Re: hardware implementation of JVM...urgent!!!! (Martin Schoeberl) 9. Re: MP3 Decoder in VHDL (music4boo (sent by Nabble.com)) 10. Re: MP3 Decoder in VHDL (Guy Hutchison) 11. Re: hardware implementation of JVM...urgent!!!! (<A HREF="http://www.opencores.org/mailman/listinfo/cores">shikhanshu at gmail.com</A>) 12. @martin... (<A HREF="http://www.opencores.org/mailman/listinfo/cores">shikhanshu at gmail.com</A>) 13. Re: @martin... (Martin Schoeberl) ---------------------------------------------------------------------- Message: 1 Date: Tue, 31 Jan 2006 06:09:12 +0100 (CET) From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">p_bharatin at yahoo.com</A> Subject: [oc] 1024 point FFT processor To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A> Message-ID: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">20060131050912.BC7A24C2A8 at www.opencores.org</A>> can anyone send me the code for the implementation of a 1024 point 16 bit fft processor ? i would be thankful to them .u can mail to my id <A HREF="http://www.opencores.org/mailman/listinfo/cores">p_bharatin at yahoo.com</A> ------------------------------ Message: 2 Date: Thu, 2 Feb 2006 21:13:33 +0100 (CET) From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">jverhoeve at gmail.com</A> Subject: [oc] ata-3 IP-core To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A> Message-ID: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">20060202201333.D49634C2AA at www.opencores.org</A>> Hello, I'm new to vhdl development, but should like to try to get the ata-3 IP-core working in a little project. ( core: <A HREF="http://www.opencores.org/projects.cgi/web/ata/overview">http://www.opencores.org/projects.cgi/web/ata/overview</A> ) But I had some questions about this one. In the cvs multiple files are available, but there is not mentioned which one is the top level one. So I don't really know if it is "controller.vhd" or "atahost.vhd". In my believe, it should be "atahost.vhd". But there are also ATA signals available next to the wishbone signals. Do I only need to handle the wishbone signals and can ignore the ata signals? Regars, Jerre ------------------------------ Message: 3 Date: Thu, 2 Feb 2006 20:52:45 +0100 From: "Richard Herveille" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">richard at herveille.net</A>> Subject: RE: [oc] ata-3 IP-core To: "'Discussion list about free open source IP cores'" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A>> Message-ID: <00c201c62832$3da028a0$<A HREF="http://www.opencores.org/mailman/listinfo/cores">660810ac at hunmobile1</A>> Content-Type: text/plain; charset="us-ascii" In the cvs multiple files are available, but there is not mentioned which one is the top level one. So I don't really know if it is "controller.vhd" or "atahost.vhd". [rih] It is atahost.vhd. In my believe, it should be "atahost.vhd". But there are also ATA signals available next to the wishbone signals. Do I only need to handle the wishbone signals and can ignore the ata signals? [rih] I suppose you want to connect a harddisk? Well at least an ATA device. If you ignore the ata signals, what are you going to connect it to?? Cheers, Richard ------------------------------ Message: 4 Date: Thu, 2 Feb 2006 23:53:18 +0100 (CET) From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">David.Wessels at gmail.com</A> Subject: Re: [oc] I2C ip core integration for ALTERA FPGAs To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A> Message-ID: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">20060202225318.2FE2A4C2AA at www.opencores.org</A>> Did you connect clock and data signals correctly? It is a bit tricky because you don't use the clock and data out lines for the actual data transfer. They are always 0. You have to use the data and output enable to make 1 and 0. Hope it is of help. Regands, David ----- Original Message ----- From: froger.e0300617 at etud.univ-ubs.fr<<A HREF="http://www.opencores.org/mailman/listinfo/cores">froger.e0300617 at e...</A>> To: Date: Tue Jan 24 20:24:08 CET 2006 Subject: [oc] I2C ip core integration for ALTERA FPGAs [q] I have the same probleme than you. I can't write in the register . For presc_HI, it is OK but for the other register, it 's always NULL. Does somebody has t this I2C master's driver files? thank you Arnaud ----- Original Message ----- From: zhangming98 at hotmail.com<zhangming98 at h...> To: Date: Wed Aug 3 06:40:08 CEST 2005 Subject: [oc] I2C ip core integration for ALTERA FPGAs [q]> Hi, Richard, Thanks for your remind, I am going to code it... > However, the core seems not working. It is no response to my[/q] IOWR [q]> (i2c_base, 0x00, 0x63) and IOWR(i2c_base, 0x01,0x00). The[/q] result of [q]> reading the 2 regs after above action is still 0xff each. I > connected the signals to Avalon Slave port according to deep below > of this[/q] email [q]> and > SCL/SDA were also instantiated.. > Kindly please advise me. > R.G > Ming[/q] ------------------------------ Message: 5 Date: Fri, 03 Feb 2006 10:44:51 +1100 From: "Mark McDougall" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">markm at vl.com.au</A>> Subject: Re: [oc] ata-3 IP-core To: Discussion list about free open source IP cores <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A>> Message-ID: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">43E29973.9000108 at vl.com.au</A>> Content-Type: text/plain; charset=ISO-8859-1; format=flowed <A HREF="http://www.opencores.org/mailman/listinfo/cores">jverhoeve at gmail.com</A> wrote: [q] In the cvs multiple files are available, but there is not mentioned which one is the top level one. So I don't really know if it is "controller.vhd" or "atahost.vhd".[/q] strangely enough, the top level is called "atahost_top.vhd" [q] In my believe, it should be "atahost.vhd". But there are also ATA signals available next to the wishbone signals. Do I only need to handle the wishbone signals and can ignore the ata signals?[/q] Read the docs (pdf) that come with the core. They are quite easy to understand and explain all you need to know about the interfaces (wishbone and ATA). Might I suggest you spend a little more time investigating what you already have at your fingertips? Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <<A HREF="http://www.vl.com.au">http://www.vl.com.au</A>> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266 ------------------------------ Message: 6 Date: Fri, 3 Feb 2006 08:52:34 +0100 (CET) From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">markus at reaaliaika.net</A> Subject: Re: [oc] Parallel Array Processor Project To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A> Message-ID: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">20060203075234.906A54C2B7 at www.opencores.org</A>> [q] hi iam searching for code or project that imoplements instruction in parallel ie., parallel procssor tht implements instructions in[/q] parallel in [q] verilog using xilinx. so plz if have ,can u post it to me. thanks sowmya [/q] Did you found the thread I started some time ago? At least the subject is exactly the same... My project (about cellular processing arrays) is going on, altought slowly, and realworld implementations might see the daylight at this century :-) Anyway, I'm doing my finally started Master Thesis about the issue. ------------------------------ Message: 7 Date: Tue, 7 Feb 2006 15:54:33 +0100 (CET) From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">shikhanshu at gmail.com</A> Subject: [oc] hardware implementation of JVM...urgent!!!! To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A> Message-ID: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">20060207145433.A978F4C2A8 at www.opencores.org</A>> hello ppl... i am working on a project which involves designing of a "hardware JVM" or a java native processor. can any1 give me any vhdl codes or any kind of headway in this regard? should i design the complete processor (complete with fetch,decode etc. units) or should i just extend the capabilities of an existing SoC? in latter case, how to do that? i would also request some1 to give me a source where i can learn the very basics of SoC, fpga etc... thanx...(its urgent) ------------------------------ Message: 8 Date: Tue, 7 Feb 2006 15:07:49 +0100 From: "Martin Schoeberl" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">martin at jopdesign.com</A>> Subject: Re: [oc] hardware implementation of JVM...urgent!!!! To: "Discussion list about free open source IP cores" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A>> Message-ID: <007001c62bef$e1e35cf0$<A HREF="http://www.opencores.org/mailman/listinfo/cores">3201a8c0 at luna</A>> Content-Type: text/plain; format=flowed; charset="iso-8859-15"; reply-type=original [q] i am working on a project which involves designing of a "hardware JVM"[/q] [q] or a java native processor. can any1 give me any vhdl codes or any kind of headway in this regard?[/q] Yep this has allready been done (e.g. Google 'Java Processor'). Ok, you can find it also at operncores: <A HREF="http://www.opencores.org/projects.cgi/web/jop/overview">http://www.opencores.org/projects.cgi/web/jop/overview</A> [q] should i design the complete processor (complete with fetch,decode etc. units) or should i just extend the capabilities of an existing[/q] SoC? [q] in latter case, how to do that? [/q] depends on your assignment ;-) Martin ------------------------------ Message: 9 Date: Tue, 7 Feb 2006 17:38:50 -0800 (PST) From: "music4boo (sent by Nabble.com)" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">lists at nabble.com</A>> Subject: Re: [oc] MP3 Decoder in VHDL To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A> Message-ID: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">2814024.post at talk.nabble.com</A>> Content-Type: text/plain; charset="us-ascii" I'm interested in testing your mp3 decoder. Could you please send me your source code? Thanks very much. Regards, Boo -- View this message in context: <A HREF="http://www.nabble.com/Re%3A-MP3-Decoder-in-VHDL-t641130.html#a2814024">http://www.nabble.com/Re%3A-MP3-Decoder-in-VHDL-t641130.html#a2814024</A> Sent from the OpenCores - IP Cores forum at Nabble.com. -------------- next part -------------- An HTML attachment was scrubbed... URL: <A HREF="http://www.opencores.org/forums.cgi/cores/attachments/20060207/1c557d49/">http://www.opencores.org/forums.cgi/cores/attachments/20060207/1c557d49/</A> attachment-0001.html ------------------------------ Message: 10 Date: Tue, 7 Feb 2006 17:44:18 -0800 From: Guy Hutchison <<A HREF="http://www.opencores.org/mailman/listinfo/cores">ghutchis at gmail.com</A>> Subject: Re: [oc] MP3 Decoder in VHDL To: music4boo <<A HREF="http://www.opencores.org/mailman/listinfo/cores">bookito at yahoo.com</A>>, Discussion list about free open source IP cores <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A>> Message-ID: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">ac9a22c00602071744m18dd80d2t30496756327c456 at mail.gmail.com</A>> Content-Type: text/plain; charset="iso-8859-1" Does anyone actually write code any more, or just ask for it to be delivered shrink-wrapped? -------------- next part -------------- An HTML attachment was scrubbed... URL: <A HREF="http://www.opencores.org/forums.cgi/cores/attachments/20060207/339db708/">http://www.opencores.org/forums.cgi/cores/attachments/20060207/339db708/</A> attachment.htm ------------------------------ Message: 11 Date: Wed, 8 Feb 2006 05:57:32 +0100 (CET) From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">shikhanshu at gmail.com</A> Subject: Re: [oc] hardware implementation of JVM...urgent!!!! To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A> Message-ID: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">20060208045732.2C7654C2A9 at www.opencores.org</A>> hi martin, thanx...but i am a newbie at this stuff and need to know the basics of fpga design using vhdl, arch of fpga, concepts of SoC before jumping in....actually i have downloaded the JOP from jopdesign.com but can't seem to get it through my head.... i need to know a step-by-step approach to designing a java processor coz i wanna work on my own... 't would be great if u could help me out with that.... thanx.... ------------------------------ Message: 12 Date: Wed, 8 Feb 2006 06:09:20 +0100 (CET) From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">shikhanshu at gmail.com</A> Subject: [oc] @martin... To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A> Message-ID: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">20060208050920.2C3E84C2A9 at www.opencores.org</A>> hello martin, i feel privileged to talk to the creator of the JOP... i don't think anybody can explain me about the design of a java processor better than you... will 2 months be enough for this work?? can u just tell me how to get started? is vhdl the only thing in which i will be writing code?? i want a very simple processor with no complex features like threading, garbage collection etc., a simple decoder to execute a subset of the bytecode....what should be my very first step? thanx... (hope u can take some time out to reply to this mail)... ---this is my final year project and i need to submit it before april--- ------------------------------ Message: 13 Date: Wed, 8 Feb 2006 22:51:22 +0100 From: "Martin Schoeberl" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">martin at jopdesign.com</A>> Subject: Re: [oc] @martin... To: "Discussion list about free open source IP cores" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A>> Message-ID: <004001c62cf9$ce5ae4e0$<A HREF="http://www.opencores.org/mailman/listinfo/cores">f3e18380 at luna</A>> Content-Type: text/plain; format=flowed; charset="iso-8859-15"; reply-type=original [q] hello martin, i feel privileged to talk to the creator of the JOP...[/q] thank you ;-) [q] will 2 months be enough for this work?? can u just tell me how to get [/q] I don't think so. It depends on your previous knowledge and how much you want to implement. If you have already done a simple processor and you only want to execute a few bytecodes that are 'fixed' in an on-chip RAM it could be possible. That's the way I started... [q] started? is vhdl the only thing in which i will be writing code??[/q] You need some way to load your Java application. The minimum is to get out the bytecodes from a single method and put it into the FPGA memory (see above). Perhaps you can use some tools from JOP for this task. [q] i want a very simple processor with no complex features like[/q] threading, [q] garbage collection etc., a simple decoder to execute a subset of the bytecode....what should be my very first step?[/q] Implement the execution unit, in the case of a Java processor a stack machine. wish you luck and some fun with your Java processor, Martin ------------------------------ _______________________________________________ Cores mailing list <A HREF="http://www.opencores.org/mailman/listinfo/cores">Cores at opencores.org</A> <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> End of Cores Digest, Vol 27, Issue 2 ************************************ Could you show me this processor calculate posibility and architecture? Processor's Architecture and FPGA development is my hobby :) Regands, Denis -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of cores-request at opencores.org Sent: Thursday, February 09, 2006 4:46 AM To: cores at opencores.org Subject: Cores Digest, Vol 27, Issue 2 Send Cores mailing list submissions to cores at opencores.org To subscribe or unsubscribe via the World Wide Web, visit http://www.opencores.org/mailman/listinfo/cores or, via email, send a message with subject or body 'help' to cores-request at opencores.org You can reach the person managing the list at cores-owner at opencores.org When replying, please edit your Subject line so it is more specific than "Re: Contents of Cores digest..." Today's Topics: 1. 1024 point FFT processor (p_bharatin at yahoo.com) 2. ata-3 IP-core (jverhoeve at gmail.com) 3. RE: ata-3 IP-core (Richard Herveille) 4. Re: I2C ip core integration for ALTERA FPGAs (David.Wessels at gmail.com) 5. Re: ata-3 IP-core (Mark McDougall) 6. Re: Parallel Array Processor Project (markus at reaaliaika.net) 7. hardware implementation of JVM...urgent!!!! (shikhanshu at gmail.com) 8. Re: hardware implementation of JVM...urgent!!!! (Martin Schoeberl) 9. Re: MP3 Decoder in VHDL (music4boo (sent by Nabble.com)) 10. Re: MP3 Decoder in VHDL (Guy Hutchison) 11. Re: hardware implementation of JVM...urgent!!!! (shikhanshu at gmail.com) 12. @martin... (shikhanshu at gmail.com) 13. Re: @martin... (Martin Schoeberl) ---------------------------------------------------------------------- Message: 1 Date: Tue, 31 Jan 2006 06:09:12 +0100 (CET) From: p_bharatin at yahoo.com Subject: [oc] 1024 point FFT processor To: cores at opencores.org Message-ID: 20060131050912.BC7A24C2A8 at www.opencores.org> can anyone send me the code for the implementation of a 1024 point 16 bit fft processor ? i would be thankful to them .u can mail to my id p_bharatin at yahoo.com ------------------------------ Message: 2 Date: Thu, 2 Feb 2006 21:13:33 +0100 (CET) From: jverhoeve at gmail.com Subject: [oc] ata-3 IP-core To: cores at opencores.org Message-ID: 20060202201333.D49634C2AA at www.opencores.org> Hello, I'm new to vhdl development, but should like to try to get the ata-3 IP-core working in a little project. ( core: http://www.opencores.org/projects.cgi/web/ata/overview ) But I had some questions about this one. In the cvs multiple files are available, but there is not mentioned which one is the top level one. So I don't really know if it is "controller.vhd" or "atahost.vhd". In my believe, it should be "atahost.vhd". But there are also ATA signals available next to the wishbone signals. Do I only need to handle the wishbone signals and can ignore the ata signals? Regars, Jerre ------------------------------ Message: 3 Date: Thu, 2 Feb 2006 20:52:45 +0100 From: "Richard Herveille" richard at herveille.net> Subject: RE: [oc] ata-3 IP-core To: "'Discussion list about free open source IP cores'" cores at opencores.org> Message-ID: 660810ac at hunmobile1> Content-Type: text/plain; charset="us-ascii" In the cvs multiple files are available, but there is not mentioned which one is the top level one. So I don't really know if it is "controller.vhd" or "atahost.vhd". [rih] It is atahost.vhd. In my believe, it should be "atahost.vhd". But there are also ATA signals available next to the wishbone signals. Do I only need to handle the wishbone signals and can ignore the ata signals? [rih] I suppose you want to connect a harddisk? Well at least an ATA device. If you ignore the ata signals, what are you going to connect it to?? Cheers, Richard ------------------------------ Message: 4 Date: Thu, 2 Feb 2006 23:53:18 +0100 (CET) From: David.Wessels at gmail.com Subject: Re: [oc] I2C ip core integration for ALTERA FPGAs To: cores at opencores.org Message-ID: 20060202225318.2FE2A4C2AA at www.opencores.org> Did you connect clock and data signals correctly? It is a bit tricky because you don't use the clock and data out lines for the actual data transfer. They are always 0. You have to use the data and output enable to make 1 and 0. Hope it is of help. Regands, David ----- Original Message ----- From: froger.e0300617 at etud.univ-ubs.frfroger.e0300617 at e...> To: Date: Tue Jan 24 20:24:08 CET 2006 Subject: [oc] I2C ip core integration for ALTERA FPGAs I have the same probleme than you. I can't write in the register . For presc_HI, it is OK but for the other register, it 's always NULL. Does somebody has t this I2C master's driver files? thank you Arnaud ----- Original Message ----- From: zhangming98 at hotmail.com To: Date: Wed Aug 3 06:40:08 CEST 2005 Subject: [oc] I2C ip core integration for ALTERA FPGAs > Hi, Richard, Thanks for your remind, I am going to code it... > However, the core seems not working. It is no response to my IOWR > (i2c_base, 0x00, 0x63) and IOWR(i2c_base, 0x01,0x00). The result of > reading the 2 regs after above action is still 0xff each. I > connected the signals to Avalon Slave port according to deep below > of this email > and > SCL/SDA were also instantiated.. > Kindly please advise me. > R.G > Ming ------------------------------ Message: 5 Date: Fri, 03 Feb 2006 10:44:51 +1100 From: "Mark McDougall" markm at vl.com.au> Subject: Re: [oc] ata-3 IP-core To: Discussion list about free open source IP cores cores at opencores.org> Message-ID: 43E29973.9000108 at vl.com.au> Content-Type: text/plain; charset=ISO-8859-1; format=flowed jverhoeve at gmail.com wrote: In the cvs multiple files are available, but there is not mentioned which one is the top level one. So I don't really know if it is "controller.vhd" or "atahost.vhd". strangely enough, the top level is called "atahost_top.vhd" In my believe, it should be "atahost.vhd". But there are also ATA signals available next to the wishbone signals. Do I only need to handle the wishbone signals and can ignore the ata signals? Read the docs (pdf) that come with the core. They are quite easy to understand and explain all you need to know about the interfaces (wishbone and ATA). Might I suggest you spend a little more time investigating what you already have at your fingertips? Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266 ------------------------------ Message: 6 Date: Fri, 3 Feb 2006 08:52:34 +0100 (CET) From: markus at reaaliaika.net Subject: Re: [oc] Parallel Array Processor Project To: cores at opencores.org Message-ID: 20060203075234.906A54C2B7 at www.opencores.org> hi iam searching for code or project that imoplements instruction in parallel ie., parallel procssor tht implements instructions in parallel in verilog using xilinx. so plz if have ,can u post it to me. thanks sowmya Did you found the thread I started some time ago? At least the subject is exactly the same... My project (about cellular processing arrays) is going on, altought slowly, and realworld implementations might see the daylight at this century :-) Anyway, I'm doing my finally started Master Thesis about the issue. ------------------------------ Message: 7 Date: Tue, 7 Feb 2006 15:54:33 +0100 (CET) From: shikhanshu at gmail.com Subject: [oc] hardware implementation of JVM...urgent!!!! To: cores at opencores.org Message-ID: 20060207145433.A978F4C2A8 at www.opencores.org> hello ppl... i am working on a project which involves designing of a "hardware JVM" or a java native processor. can any1 give me any vhdl codes or any kind of headway in this regard? should i design the complete processor (complete with fetch,decode etc. units) or should i just extend the capabilities of an existing SoC? in latter case, how to do that? i would also request some1 to give me a source where i can learn the very basics of SoC, fpga etc... thanx...(its urgent) ------------------------------ Message: 8 Date: Tue, 7 Feb 2006 15:07:49 +0100 From: "Martin Schoeberl" martin at jopdesign.com> Subject: Re: [oc] hardware implementation of JVM...urgent!!!! To: "Discussion list about free open source IP cores" cores at opencores.org> Message-ID: 3201a8c0 at luna> Content-Type: text/plain; format=flowed; charset="iso-8859-15"; reply-type=original i am working on a project which involves designing of a "hardware JVM" or a java native processor. can any1 give me any vhdl codes or any kind of headway in this regard? Yep this has allready been done (e.g. Google 'Java Processor'). Ok, you can find it also at operncores: http://www.opencores.org/projects.cgi/web/jop/overview should i design the complete processor (complete with fetch,decode etc. units) or should i just extend the capabilities of an existing SoC? in latter case, how to do that? depends on your assignment ;-) Martin ------------------------------ Message: 9 Date: Tue, 7 Feb 2006 17:38:50 -0800 (PST) From: "music4boo (sent by Nabble.com)" lists at nabble.com> Subject: Re: [oc] MP3 Decoder in VHDL To: cores at opencores.org Message-ID: 2814024.post at talk.nabble.com> Content-Type: text/plain; charset="us-ascii" I'm interested in testing your mp3 decoder. Could you please send me your source code? Thanks very much. Regards, Boo -- View this message in context: http://www.nabble.com/Re%3A-MP3-Decoder-in-VHDL-t641130.html#a2814024 Sent from the OpenCores - IP Cores forum at Nabble.com. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20060207/1c557d49/ attachment-0001.html ------------------------------ Message: 10 Date: Tue, 7 Feb 2006 17:44:18 -0800 From: Guy Hutchison ghutchis at gmail.com> Subject: Re: [oc] MP3 Decoder in VHDL To: music4boo bookito at yahoo.com>, Discussion list about free open source IP cores cores at opencores.org> Message-ID: ac9a22c00602071744m18dd80d2t30496756327c456 at mail.gmail.com> Content-Type: text/plain; charset="iso-8859-1" Does anyone actually write code any more, or just ask for it to be delivered shrink-wrapped? -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20060207/339db708/ attachment.htm ------------------------------ Message: 11 Date: Wed, 8 Feb 2006 05:57:32 +0100 (CET) From: shikhanshu at gmail.com Subject: Re: [oc] hardware implementation of JVM...urgent!!!! To: cores at opencores.org Message-ID: 20060208045732.2C7654C2A9 at www.opencores.org> hi martin, thanx...but i am a newbie at this stuff and need to know the basics of fpga design using vhdl, arch of fpga, concepts of SoC before jumping in....actually i have downloaded the JOP from jopdesign.com but can't seem to get it through my head.... i need to know a step-by-step approach to designing a java processor coz i wanna work on my own... 't would be great if u could help me out with that.... thanx.... ------------------------------ Message: 12 Date: Wed, 8 Feb 2006 06:09:20 +0100 (CET) From: shikhanshu at gmail.com Subject: [oc] @martin... To: cores at opencores.org Message-ID: 20060208050920.2C3E84C2A9 at www.opencores.org> hello martin, i feel privileged to talk to the creator of the JOP... i don't think anybody can explain me about the design of a java processor better than you... will 2 months be enough for this work?? can u just tell me how to get started? is vhdl the only thing in which i will be writing code?? i want a very simple processor with no complex features like threading, garbage collection etc., a simple decoder to execute a subset of the bytecode....what should be my very first step? thanx... (hope u can take some time out to reply to this mail)... ---this is my final year project and i need to submit it before april--- ------------------------------ Message: 13 Date: Wed, 8 Feb 2006 22:51:22 +0100 From: "Martin Schoeberl" martin at jopdesign.com> Subject: Re: [oc] @martin... To: "Discussion list about free open source IP cores" cores at opencores.org> Message-ID: f3e18380 at luna> Content-Type: text/plain; format=flowed; charset="iso-8859-15"; reply-type=original hello martin, i feel privileged to talk to the creator of the JOP... thank you ;-) will 2 months be enough for this work?? can u just tell me how to get I don't think so. It depends on your previous knowledge and how much you want to implement. If you have already done a simple processor and you only want to execute a few bytecodes that are 'fixed' in an on-chip RAM it could be possible. That's the way I started... started? is vhdl the only thing in which i will be writing code?? You need some way to load your Java application. The minimum is to get out the bytecodes from a single method and put it into the FPGA memory (see above). Perhaps you can use some tools from JOP for this task. i want a very simple processor with no complex features like threading, garbage collection etc., a simple decoder to execute a subset of the bytecode....what should be my very first step? Implement the execution unit, in the case of a Java processor a stack machine. wish you luck and some fun with your Java processor, Martin ------------------------------ _______________________________________________ Cores mailing list Cores at opencores.org http://www.opencores.org/mailman/listinfo/cores End of Cores Digest, Vol 27, Issue 2 ************************************

Parallel Array Processor Project by Unknown on Mar 30, 2006			Not available!
----- Original Message ----- From: Joachim StrÃ¶mbergson<<A HREF="http://www.opencores.org/mailman/listinfo/cores">Joachim.Strombergson at I...</A>> To: Date: Tue Aug 17 09:21:15 CEST 2004 Subject: [oc] Parallel Array Processor Project [q] Aloha! <A HREF="http://www.opencores.org/mailman/listinfo/cores">markus at r...</A> wrote: [q]> Have anyone programmed DSPs with C (or other higher level [/q] language)? [q]> In my other project, a DSP-based guitar effect box, I'm [/q] programming [q]> Motorola DSP56303. It's very hard to try to express variable [/q] allocation [q]> from different kinds of memories (internal/external, X/Y/P/L) [/q] and it's very [q]> hard to write a good C compiler for these. And trying to write [/q] an OS: [q]> very unpleasant job, indeed. [/q] Yes I have. I would say that quite a lot (most?) DSP programming is done in C, albeit with more or less lots of pragmas and calls to (inlined) library functions sprinkled whithin the code. DSP codes are much more regular with the bulk of the execution located in specific kernels. The kernels however might be written in optimized assembler for the specific architecture. Programming DSPs can be quite a challenge, both due to non-orthogonal instruction sets and (for example TIs 6000 series) VLIW and multiple core architectures. TI, AMD, AD etc spends lots of money developing good compilers for their architectures. [q]> There were one idea I haven't even think about - constructing [/q] a stack- [q]> based PSM. The author has rejected this because it's not very > straightforward to program, but that doesn't matter in this [/q] project. Stack based cores for embedded multiprocessor applications are a very fine idea. There have been some work done on this, but I have few references for you. One thing to consider is how to implement/include the communication semantics. You could do this by adding a communication co-processor that extends the instruction set with port semantics. Doing this pushes/exposes the syncronization to the user and removes lots of burden for the HW implementation. [q]> The compiler could be easily modified to output reverse polish [/q] program [q]> for the cell. In fact, it's easier to do this than make the [/q] compiler to [q]> output programs for register-based PSMs. [/q] You mean you have a pcode generator? ;-) [q]> The stack-based PSM would have a very dense instruction set [/q] and it [q]> would be versatile with small efforts. [/q] Yep! -- Med vÃ¤nlig hÃ¤lsning, Yours Joachim StrÃ¶mbergson - Alltid i harmonisk svÃ¤ngning. VP, Research & Development -------------------------------------------------------------------[/q] --- [q] InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÃ–TEBORG / Sweden Tel: +46 31 68 54 90 Fax: +46 31 68 54 91 Mobile: +46 733 75 97 02 E-mail: <A HREF="http://www.opencores.org/mailman/listinfo/cores">joachim.strombergson at i...</A> Home: www.informasic.com -------------------------------------------------------------------[/q] --- [q] [/q] ----- Original Message ----- From: Joachim StrÃ¶mbergsonJoachim.Strombergson at I...> To: Date: Tue Aug 17 09:21:15 CEST 2004 Subject: [oc] Parallel Array Processor Project Aloha! markus at r... wrote: > Have anyone programmed DSPs with C (or other higher level language)? > In my other project, a DSP-based guitar effect box, I'm programming > Motorola DSP56303. It's very hard to try to express variable allocation > from different kinds of memories (internal/external, X/Y/P/L) and it's very > hard to write a good C compiler for these. And trying to write an OS: > very unpleasant job, indeed. Yes I have. I would say that quite a lot (most?) DSP programming is done in C, albeit with more or less lots of pragmas and calls to (inlined) library functions sprinkled whithin the code. DSP codes are much more regular with the bulk of the execution located in specific kernels. The kernels however might be written in optimized assembler for the specific architecture. Programming DSPs can be quite a challenge, both due to non-orthogonal instruction sets and (for example TIs 6000 series) VLIW and multiple core architectures. TI, AMD, AD etc spends lots of money developing good compilers for their architectures. > There were one idea I haven't even think about - constructing a stack- > based PSM. The author has rejected this because it's not very > straightforward to program, but that doesn't matter in this project. Stack based cores for embedded multiprocessor applications are a very fine idea. There have been some work done on this, but I have few references for you. One thing to consider is how to implement/include the communication semantics. You could do this by adding a communication co-processor that extends the instruction set with port semantics. Doing this pushes/exposes the syncronization to the user and removes lots of burden for the HW implementation. > The compiler could be easily modified to output reverse polish program > for the cell. In fact, it's easier to do this than make the compiler to > output programs for register-based PSMs. You mean you have a pcode generator? ;-) > The stack-based PSM would have a very dense instruction set and it > would be versatile with small efforts. Yep! -- Med vÃ¤nlig hÃ¤lsning, Yours Joachim StrÃ¶mbergson - Alltid i harmonisk svÃ¤ngning. VP, Research & Development ------------------------------------------------------------------- --- InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÃ–TEBORG / Sweden Tel: +46 31 68 54 90 Fax: +46 31 68 54 91 Mobile: +46 733 75 97 02 E-mail: joachim.strombergson at i... Home: www.informasic.com ------------------------------------------------------------------- ---

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