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RE: SD Controller and plb-wb bridge
by bhupesh.suitcasetv on Oct 30, 2009 |
bhupesh.suitcasetv
Posts: 27 Joined: Apr 15, 2009 Last seen: Nov 22, 2013 |
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what are the .c & .h files should i use, i don't have much of exposure to C. when i tried to compile the main.c in NIOS IDE it gave some errors like below
../BootReset.S:169: Error: unrecognised instruction l.nop........ I have changed void start() to void main(). would appriciate any help from people who have done before or know how to do....# |
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RE: SD Controller and plb-wb bridge
by tac2 on Oct 30, 2009 |
tac2
Posts: 27 Joined: Sep 23, 2008 Last seen: Feb 3, 2025 |
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what are the .c & .h files should i use, i don't have much of exposure to C. when i tried to compile the main.c in NIOS IDE it gave some errors like below
../BootReset.S:169: Error: unrecognised instruction l.nop........ I have changed void start() to void main(). would appriciate any help from people who have done before or know how to do....# You have make alots of modiciations in the main.c file, i think its better to make new one then just include the sd_contoller.c and .h or copy in the instructions. The main file contains some board specific operations which is not necessary in NIOS. |
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RE: SD Controller and plb-wb bridge
by bhupesh.suitcasetv on Nov 3, 2009 |
bhupesh.suitcasetv
Posts: 27 Joined: Apr 15, 2009 Last seen: Nov 22, 2013 |
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Hi,
I have implemented the TX and RX FIFO using altera megafunction, as with the given FIFO i was getting the synthesis error. will the core works in hardware with these changes?? when i tried to simulate the code with alttera FIFOs the simulation give's an error....my worry is after spending so much time on running the code in modelsim, the doing synthesis...i don't like it to fail in hardware.....any input and sugessions appreciated. Thanks |
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RE: SD Controller and plb-wb bridge
by tac2 on Nov 4, 2009 |
tac2
Posts: 27 Joined: Sep 23, 2008 Last seen: Feb 3, 2025 |
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What is wrong with the FIFO at the synthesis, it worked here in Quartus 9.0. But i guess a altera specific FIFO should work as well.
Post here what's going wrong in the simulation |
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RE: SD Controller and plb-wb bridge
by bhupesh.suitcasetv on Nov 4, 2009 |
bhupesh.suitcasetv
Posts: 27 Joined: Apr 15, 2009 Last seen: Nov 22, 2013 |
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orignal fifo code does get synthesise in altera quartus 9.0 but when u see the resource utilazation by entity....tx fifo is implemented half of the depth specified in sd_defines
i have set the below parameters `define FIFO_RX_MEM_DEPTH 512 `define FIFO_RX_MEM_ADR_SIZE 9 `define FIFO_TX_MEM_DEPTH 512 `define FIFO_TX_MEM_ADR_SIZE 9 for tx fifo the tool has implemented 8192 bits of memory and for rx fifo it gives an warning of latches implemented for tmp & ft. any idea why the quartus does not implement fifo for rx?? Thanks |
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RE: SD Controller and plb-wb bridge
by tac2 on Nov 4, 2009 |
tac2
Posts: 27 Joined: Sep 23, 2008 Last seen: Feb 3, 2025 |
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orignal fifo code does get synthesise in altera quartus 9.0 but when u see the resource utilazation by entity....tx fifo is implemented half of the depth specified in sd_defines
i have set the below parameters `define FIFO_RX_MEM_DEPTH 512 `define FIFO_RX_MEM_ADR_SIZE 9 `define FIFO_TX_MEM_DEPTH 512 `define FIFO_TX_MEM_ADR_SIZE 9 for tx fifo the tool has implemented 8192 bits of memory and for rx fifo it gives an warning of latches implemented for tmp & ft. any idea why the quartus does not implement fifo for rx?? Thanks The MEM_ADR_SIZE should acutely be 1 bit bigger, the MSB of the address is used for FIFO flag calculation. This should probably be changed... But try to change to 10 maybe Quartus optimized away the rest of the bits. BTW that big RAM shouldn't be necessary if you don't have a really slow system RAM. |
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RE: SD Controller and plb-wb bridge
by bhupesh.suitcasetv on Nov 6, 2009 |
bhupesh.suitcasetv
Posts: 27 Joined: Apr 15, 2009 Last seen: Nov 22, 2013 |
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Hi,
I have come to a point where i can debug the C code in NIOS IDE. I am attaching the C codes.
In one of the document i have read that signals to SD card shall be pulled up(other than clk)??
when i send a simple command 0 wih argument 0 i get the bit 0 set to '0 in normal response register....does that mean the SD card has not received the command properly??
i am stuck in the start of the program it self.....
href="uploads/1257502374_sd_controller.c">sd_controller.c (5 kb)
main.c (14 kb)
sd_controller.h (3 kb)
sd_controller.c (5 kb)
orsocdef.h (5 kb)
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RE: SD Controller and plb-wb bridge
by tac2 on Nov 6, 2009 |
tac2
Posts: 27 Joined: Sep 23, 2008 Last seen: Feb 3, 2025 |
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Hello.
I suggest that u after the intital sequence. IOWR(SD_TOP_0_BASE,SD_TIMEOUT,0x000009C4); IOWR(SD_TOP_0_BASE,SD_SOFTWARE_RST,0x00000001); IOWR(SD_TOP_0_BASE,SD_CLOCK_D,0x00000000); IOWR(SD_TOP_0_BASE,SD_SOFTWARE_RST,0x00000000); Do a readback on the Timeout and Reset register so you know it has been set and that the communication working properly. The bit should be 1 when the command has been sent. What's the output from the get_rca loop? |
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RE: SD Controller and plb-wb bridge
by bhupesh.suitcasetv on Nov 6, 2009 |
bhupesh.suitcasetv
Posts: 27 Joined: Apr 15, 2009 Last seen: Nov 22, 2013 |
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some improvement....every thing fine until i send command 8....after i send command 8...i get normal response value as 0x8000 and error response register value as 0x0001(command timeout error)...how do i resolve this issue??
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RE: SD Controller and plb-wb bridge
by tac2 on Nov 6, 2009 |
tac2
Posts: 27 Joined: Sep 23, 2008 Last seen: Feb 3, 2025 |
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If you get timeout on CMD8 it means that you are using a older SD card, which doesn't respond to this. So when you get a time-out, send a new reset command to the card and do the init sequence again but this time skip command 8.
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RE: SD Controller and plb-wb bridge
by bhupesh.suitcasetv on Nov 10, 2009 |
bhupesh.suitcasetv
Posts: 27 Joined: Apr 15, 2009 Last seen: Nov 22, 2013 |
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here is a sequence of my program
1.SD_timeout 0x9c4 2.soft reset 3.clock 0x8 i am running at low speed my input is 100MHz 4.deassert soft reset 5.command 0 with argument 0 6.command 8 7.command timeout error, Error Interrupt Status Reg = 0x00000001 & Normal Interrupt Status Reg = 0x00008000 8.repeat step 1 to 5 9. command 55 response 0x00000120, no errors 10. command ACMD41 response 0x00ff8000 but with command timeout error, Error Interrupt Status Reg = 0x00000001 & Normal Interrupt Status Reg = 0x00008000 what should i do now...???? |
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RE: SD Controller and plb-wb bridge
by tac2 on Nov 10, 2009 |
tac2
Posts: 27 Joined: Sep 23, 2008 Last seen: Feb 3, 2025 |
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I think ACMD41 takes longer to respond, try increase the time-out to the max h'FFF. Otherwise the responses looks good.
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RE: SD Controller and plb-wb bridge
by bhupesh.suitcasetv on Nov 10, 2009 |
bhupesh.suitcasetv
Posts: 27 Joined: Apr 15, 2009 Last seen: Nov 22, 2013 |
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i tried increasing the time out to 0xfff and also to 0x3fff...but sam result....but i thing which i have observed is that the Status Register value is 0x3000 when i send command 8 and command ACMD41...and on these two commands the command timeout error comes...any idea what is going wrong...???
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RE: SD Controller and plb-wb bridge
by tac2 on Nov 10, 2009 |
tac2
Posts: 27 Joined: Sep 23, 2008 Last seen: Feb 3, 2025 |
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Ok, if its stuck in h'3000 it means that the controller is busy waiting for a reply.
We change the reset behaviour before... It might have something to do with that the controller doesn't reset properly after a time-out. Check the status-register after you get the first time-out on CMD8... Can you please upload the modified top and cmd_serial_host to me thanks. |
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RE: SD Controller and plb-wb bridge
by bhupesh.suitcasetv on Nov 11, 2009 |
bhupesh.suitcasetv
Posts: 27 Joined: Apr 15, 2009 Last seen: Nov 22, 2013 |
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Hi,
Pls. find the files attached. Regards, Bhupesh
SD_cmd_serial_host_.v (12 kb)
SD_controller_top.v (16 kb)
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