No, how did you do with the FIFO? Did u use alteras or the one from the project? Because the FIFO in SD_BD is a bit special, it require two 32 bit writes before the non-empty flag sets.

No, how did you do with the FIFO? Did u use alteras or the one from the project? Because the FIFO in SD_BD is a bit special, it require two 32 bit writes before the non-empty flag sets.

The quartus fitter has not implemented any fifo for SD_BD, it has implemented FIFO for only TX & RX data fifo's. i have put some signal tap on internal signals and found that wishbone master sends the read address to read the data from the internal memory and kept on sending in a loop for 512 times.....i have tapped the transmit fifo full signal...it goes high after 512 clock cycles(as fifo has a dept of 512)....i will try to see what more i can find

Amir,

I've never added a custom core to Xilinx Platform Studio before, I don't suppose you could go over quickly how to bring both the SD Controller and plb-wb bridge into an XPS project?

I fear I'm going to spend a lot of time troubleshooting simple mistakes instead of verifying hardware.

Dan

Alright, since asking my last question I've gotten a little further.

I've added plbv46_2_wb to my XPS project and then added an sd_controller_fifo_wb core as well. I wired everything up; however when I try to build the netlist, it is crapping out on me because the port widths do not match between the SD Core and the bus bridge.

What is the proper way to handle this? Should I be wrapping the SD core to expose it with 32-bit data bus and a 32-bit address bus even though its not used internally in the core? If there is only one peripheral on the WB bus, do I need to do any address decoding in a wrapper module or will everything just work with the signals connected between the two cores?

Thanks,
Dan

Hi tac2,

I am back to test SD controller in hardware. when i set up the TX BD, i see that the controller is getting stuck in CMD24 response, do you have any idea what can be the issue? i am debugging it will give u more details about it

when i read SD_RESP1 register after writing into BD i get 00400900h value one more thing i have observed is that after sending CMD24 by controller the card does not response with cmd_data_i = '0', so controller time out, any idea why?

Hi Tac,

Good news now i have code which is synthesiable in altera cyclone III fpga, i have tested it with by building a system using NIOS II processor.

I have made some changes to the original code to make it work in hardware.

Thanks for the support.

bhupesh

Hi Tac,

Good news now i have code which is synthesiable in altera cyclone III fpga, i have tested it with by building a system using NIOS II processor.

I have made some changes to the original code to make it work in hardware.

Thanks for the support.

bhupesh

Hi, amir.dadjoo

I am involved in the same problems when i initialite the SD card. The busy bit is always 0 when ACMD41 is sent. How did you resolve the problem? Can you explain the method concretely?

Thanks first.

Hi,bhupesh.suitcasetv

I am involved in the same problems when i initialite the SD card. The busy bit is always 0 when ACMD41 is sent. How did you resolve the problem? Can you explain the method concretely?

Thanks first.

Hi, tac2

I am involved in the same problems when i initialite the SD card. The busy bit(bit[31]) in the response is always 0 when ACMD41 is sent,but the other response bits except bit[31] are OK. In fact,I send CMD55+ACMD41 loop. How can I solve the problem?

I am attaching an c file which initializes SD card and writes to and read from SD card.

As far as ur problem looks u have to keep on issuing CMD55 & ACMD41 till u get response from SD card.

look how i have done it C code, look into sd_controller.c

it can be a hardware problem....check that io standard in 3.3V and data and command lines have 51K pull-up resistors

Hi,bhupesh.suitcasetv

Thanks for your reply.

I reviewed your C code. The difference between your code and mine is only phys_spec_2_0. My tese card is support for SD2.0.

I checked my PCB as for your suggestion. The voltage supply and 51k pll-up are all OK.

The frequency of my controller is working in 25MHz. I guess maybe it is the problem. I get that the frequency for the initialization should be 100KHz to 400KHz.

What's your configuration about frequency in intialization and data transfer?

Thanks.