3/3 
|
Winning with a reconfigurable computer
by Unknown on Sep 8, 2004 |
Not available! | ||
|
Well i have heard those Xtensa guys.
You basically a 5-stage pipeline processor, and you get to write down the application-specific instructions running on specialized units. You write them in a kind of data-flow language (don't recall the name) and Verilog is generated. These units are placed at the execution (the 3rd) stage of the processor. I'm not aware if the processor template assumes pluging hardware accelerators interfaced through a bus (Wishbone, AMBA). In their publications, advanced instruction generation and selection algorithms have been presented. Mostly in papers of 2002 and after.
Anyway, the mentioned article talks about behavioral synthesis, a hard issue. I'm not sure they have developed their technology or it is just a small step of the above execution unit synthesis.
AFAIK behavioral synthesis results in 5x-10x less performance than hand-coding. I take examples of Celoxica and Confluence generated RTLs. Both techniques are impressive in the authenticity of approach, not performance (yet).
What is a real possibility is to use "portable RTL". The traditional RTL approach, with records for input/output ports (now acceptable by common synthesis tools), let the synthesis tool decide the addition/multiplication hardware topology etc. This works within 10-15% of optimized coding for ASIC, but less for FPGA targets.
regards
Nikolaos Kavvadias
nkavv[at]skiathos.physics.auth.gr
-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://www.opencores.org/forums.cgi/cores/attachments/20040908/ca35e028/attachment.htm
|
|||
|
Winning with a reconfigurable computer
by Unknown on Sep 8, 2004 |
Not available! | ||
|
This stuff is pretty cool. It might be a good way to compile some DSP
programs into hardware in a seamless flow. I haven't looked at it that closely, but I bet if we do, we'll find that they aren't yet compiling C data structures into multiple memories, and that many algorithms will be limited by memory access speeds. Does anyone know if they support compilation of global arrays into separate memories? That might be enough for me to make use of. Bill On Wed, 2004-09-08 at 01:06, Ricky Nite wrote:
some related news..
http://www.us.design-reuse.com/news/news8597.html
Tensilica Announces Major IC Design Automation Breakthrough, The
Automatic Generation of Optimized Programmable RTL Engines from
Standard C Code
Automates RTL Block Design; Adds Flexibility through Programmability
SANTA CLARA, Calif. - Sept. 6, 2004 - Tensilica(R), Inc. today
announced that it has achieved a major design automation breakthrough
- the automated design of optimized configurable processors from
standard C code using the company's new XPRES (Xtensa(R) PRocessor
Extension Synthesis) compiler. This tool enables the rapid development
of optimized system-on-chip (SOC) devices without requiring designers
to hand code their hardware using design languages like VHDL and
Verilog, which take months of design and verification effort.
Instead, designers input the original algorithm that they're trying to
optimize, written in standard ANSI C/C++, and the XPRES compiler,
coupled with Tensilica's automated processor generation technology,
automatically generates an RTL (register transfer level) hardware
description and associated software tool chain. In less than an hour,
the resulting hardware block is delivered in the form of a
pre-verified Xtensa LX processor core, enabling customers to future
proof their designs due to its inherent programmability, and avoid the
cost and risk associated with verifying custom logic. Additionally,
the generated RTL fully rivals the performance and efficiency of
hand-coded RTL blocks with many concurrent operations, efficient data
types, and optimized multiple wide deep pipelines.
http://www.us.design-reuse.com/news/news8597.html
__________________________________________________
Do You Yahoo!?
Tired of spam? Yahoo! Mail has the best spam protection around
http://mail.yahoo.com
______________________________________________________________________
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
|
|||
3/3