OpenCores
Home » All forums » Cores » Verilog code for DDR SDRAM Controller Core
First Prev 2/2 no use no use
RE: Verilog code for DDR SDRAM Controller Core
by dgisselq on Dec 27, 2017 		dgisselq
Posts: 247
Joined: Feb 20, 2015
Last seen: Jul 15, 2022
Is this the project you are looking for? The VHDL sources are posted with the project. What are you missing? The Xilinx generated MIG IP? You can find instructions to build that within the Mig_Settings directory.
Dan
RE: Verilog code for DDR SDRAM Controller Core
by aikijw on Dec 27, 2017 		aikijw
Posts: 76
Joined: Oct 21, 2011
Last seen: Jul 8, 2023
LOL... The OP needs the code in Verilog... His/her class isn't using VHDL... (Happy Holidays, BTW!)

First Prev 2/2 no use no use
© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.