Hi,

I have been using the design and I am having trouble with it when I
try to perform post-place and route simulations. I have created a UCF
file under Xilinx ISE6.1 and am using my own test bench. The problem
that arises is when I am trying to receive frames. I am informed that
setup violations have occurred - usually on signals in the wishdone
part. I have tested my setup using a normal simulation and the
system receives and transmits frames without a problem. Also, when I
run post-place and route simulations without a constraints file, it
all works correctly. Has anyone else had a similiar problem before or
does someone know where I should start looking to see where the
problem might be,

Thanks,
Eoin

PS, here is the constraints file that I am using:

NET "mcrs_pad_i" LOC = "P9";
NET "mcoll_pad_i" LOC = "R9";
NET "mtxd_pad_o" LOC = "K10";
NET "mtxd_pad_o" LOC = "L10";
NET "mtxd_pad_o" LOC = "K9";
NET "mtxd_pad_o" LOC = "L9";
NET "mtxerr_pad_o" LOC = "R10";
NET "mtxen_pad_o" LOC = "P10";
NET "mrxd_pad_i" LOC = "M10";
NET "mrxd_pad_i" LOC = "N10";
NET "mrxd_pad_i" LOC = "M9";
NET "mrxd_pad_i" LOC = "N9";
NET "mrxdv_pad_i" LOC = "P8";
NET "mrxerr_pad_i" LOC = "R8";
NET "mrx_clk_pad" LOC = "H17";
NET "mtx_clk_pad" LOC = "E17";
NET "wb_clk" LOC = "AK19";
NET "mdc_pad_o" LOC = "T8";
NET "md_pad_io" LOC = "U8";
TIMESPEC "TS_wb_clk" = PERIOD "wb_clk" 50 MHz HIGH 50 %;
NET "mrx_clk_pad" TNM_NET = "mrx_clk_pad";
TIMESPEC "TS_mrx_clk_pad" = PERIOD "mrx_clk_pad" 25 MHz HIGH 50 %;
NET "mtx_clk_pad" TNM_NET = "mtx_clk_pad";
TIMESPEC "TS_mtx_clk_pad" = PERIOD "mtx_clk_pad" 25 MHz HIGH 50 %;
NET "wb_clk" TNM_NET = "wb_clk";