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Underrun and RX issues
by Unknown on Jul 22, 2004 |
Not available! | ||
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Folks,
I have been working on a 10/100BaseT project using a National DP83847 and a Altera Cyclone 1C12 running at 50Mhz using the Opencores MAC. I am using Altera's plugs library for the TCP stack. I have made the changes in igor.c and igor.h to accommodate the National PHY. The MAC PHY combination will auto-negotiate at 100Mbps, Full duplex fine. Furthermore, I seem to be able to read or write to the registers of the PHY just fine. I have used the register dump routines to look at the PHY registers. They reflect the values that I would expect. The problem occurs when I try to TX or RX on packets. Every TX packet reports an under run. However, when I look at the packet that plugs is sending it is the correct length and has the correct content. The other issue is that I have never been able to see a received packet. I see the PHY TX and RX light blink but Ethereal connected to the network shows no packets from the device. No debug information comes up on the console port either. Has anyone on the list had these problems? If so how did you solve it? Does anyone have any suggestions? Any help would be appreciated. Thanks in advance for any help, Jeff Ballif |
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Underrun and RX issues
by Unknown on Aug 4, 2004 |
Not available! | ||
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Buy one of our uKit boards (see www.microtronix.com). While this ships with
an MoreThanIp core, we could provide a NIOS II core supporting the OC EMAC.
We have had good success with the EMAC but have observed problems Rx
problems at slow 33/50MHz NIOS clock rates when connected to the ethernet
MAC configured for 100Mbps. Try your board at 10Mbps, it should run fine.
Our uKit board runs the NIOS II processor at over 110 MHz and supports the
100Mbps EMAC just fine.
-----Original Message-----
From: ethmac-bounces@opencores.org
[mailto:ethmac-bounces@opencores.org]On Behalf Of
jballif@lonepeaklabs.com
Sent: Thursday, July 22, 2004 2:06 PM
To: ethmac@opencores.org
Subject: [ethmac] Underrun and RX issues
Folks,
I have been working on a 10/100BaseT project using a National DP83847
and a Altera Cyclone 1C12 running at 50Mhz using the Opencores MAC.
I am using Altera's plugs library for the TCP stack. I have made the
changes in igor.c and igor.h to accommodate the National PHY. The MAC
PHY combination will auto-negotiate at 100Mbps, Full duplex fine.
Furthermore, I seem to be able to read or write to the registers of
the PHY just fine. I have used the register dump routines to look at
the PHY registers. They reflect the values that I would expect. The
problem occurs when I try to TX or RX on packets. Every TX packet
reports an under run. However, when I look at the packet that plugs
is sending it is the correct length and has the correct content. The
other issue is that I have never been able to see a received packet.
I see the PHY TX and RX light blink but Ethereal connected to the
network shows no packets from the device. No debug information comes
up on the console port either. Has anyone on the list had these
problems? If so how did you solve it? Does anyone have any
suggestions? Any help would be appreciated.
Thanks in advance for any help,
Jeff Ballif
_______________________________________________
http://www.opencores.org/mailman/listinfo/ethmac
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Underrun and RX issues
by Unknown on Aug 4, 2004 |
Not available! | ||
|
Norm,
what kind of problems do you observed in 100Mbps with the OpenCores MAC? Best Regards, Marc At 10:55 04.08.2004 -0400, you wrote:
Buy one of our uKit boards (see www.microtronix.com). While this ships with
an MoreThanIp core, we could provide a NIOS II core supporting the OC EMAC.
We have had good success with the EMAC but have observed problems Rx
problems at slow 33/50MHz NIOS clock rates when connected to the ethernet
MAC configured for 100Mbps. Try your board at 10Mbps, it should run fine.
Our uKit board runs the NIOS II processor at over 110 MHz and supports the
100Mbps EMAC just fine.
-----Original Message-----
From: ethmac-bounces@opencores.org
[mailto:ethmac-bounces@opencores.org]On Behalf Of
jballif@lonepeaklabs.com
Sent: Thursday, July 22, 2004 2:06 PM
To: ethmac@opencores.org
Subject: [ethmac] Underrun and RX issues
Folks,
I have been working on a 10/100BaseT project using a National DP83847
and a Altera Cyclone 1C12 running at 50Mhz using the Opencores MAC.
I am using Altera's plugs library for the TCP stack. I have made the
changes in igor.c and igor.h to accommodate the National PHY. The MAC
PHY combination will auto-negotiate at 100Mbps, Full duplex fine.
Furthermore, I seem to be able to read or write to the registers of
the PHY just fine. I have used the register dump routines to look at
the PHY registers. They reflect the values that I would expect. The
problem occurs when I try to TX or RX on packets. Every TX packet
reports an under run. However, when I look at the packet that plugs
is sending it is the correct length and has the correct content. The
other issue is that I have never been able to see a received packet.
I see the PHY TX and RX light blink but Ethereal connected to the
network shows no packets from the device. No debug information comes
up on the console port either. Has anyone on the list had these
problems? If so how did you solve it? Does anyone have any
suggestions? Any help would be appreciated.
Thanks in advance for any help,
Jeff Ballif
_______________________________________________
http://www.opencores.org/mailman/listinfo/ethmac
_______________________________________________
http://www.opencores.org/mailman/listinfo/ethmac
MaCo-Engineering
Dipl.-Ing. Marc Colling
Schlossstrasse 50
66352 Karlsbrunn
GERMANY
phone : (+49) 6809 / 7020190
fax : (+49) 6809 / 7020191
mobile : (+49) 170 / 7780788
Marc.Colling@MaCo-Engineering.de
www.MaCo-Engineering.de
|
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Underrun and RX issues
by Unknown on Aug 9, 2004 |
Not available! | ||
|
I understand the Opencores Emac Dma's data directly between memory and the
ethernet wire, with minimal (about 12 bytes, I believe) on chip buffering.
This amounts to "essentially" unbuffered transfers have to contend with
other concurrent NIOS bus and memory activities, such as instruction
fetches, memory accesses of the currently executing instruction, and any
other DMA operations (including a possible second simultaneous full duplex
Emac transfer). Excessive contention causes EMAC receive overruns and
transmit underruns.
The number of memory wait states almost certainly increases the risk of the
EMAC's DMA falling behind (we did conduct a few SDRAM versus SRAM tests, but
with inconclusive results).
Our experience has been that at least a 44 MHz core using the so called
"old" memory controller is required for reasonably adequate SDRAM operation
on a 100 mbit ethernet; with the so called "new" memory controller, it seems
that a 50 MHz core is too slow; 75 MHz appears adequate.
Our tests with cores running beneath the threshold clock frequency incurred
Rx overruns and Tx underruns; some of the DMA transfers that did not
over/under run were observed to corrupt the data being transferred.
Regards
Norm
-----Original Message-----
From: ethmac-bounces@opencores.org
[mailto:ethmac-bounces@opencores.org]On Behalf Of Marc Colling
Sent: Wednesday, August 04, 2004 11:18 AM
To: List about open source Ethernet MAC core
Subject: RE: [ethmac] Underrun and RX issues
Norm,
what kind of problems do you observed in 100Mbps with the OpenCores MAC?
Best Regards,
Marc
At 10:55 04.08.2004 -0400, you wrote:
Buy one of our uKit boards (see www.microtronix.com). While this ships with
an MoreThanIp core, we could provide a NIOS II core supporting the OC EMAC.
We have had good success with the EMAC but have observed problems Rx
problems at slow 33/50MHz NIOS clock rates when connected to the ethernet
MAC configured for 100Mbps. Try your board at 10Mbps, it should run fine.
Our uKit board runs the NIOS II processor at over 110 MHz and supports the
100Mbps EMAC just fine.
-----Original Message-----
From: ethmac-bounces@opencores.org
[mailto:ethmac-bounces@opencores.org]On Behalf Of
jballif@lonepeaklabs.com
Sent: Thursday, July 22, 2004 2:06 PM
To: ethmac@opencores.org
Subject: [ethmac] Underrun and RX issues
Folks,
I have been working on a 10/100BaseT project using a National DP83847
and a Altera Cyclone 1C12 running at 50Mhz using the Opencores MAC.
I am using Altera's plugs library for the TCP stack. I have made the
changes in igor.c and igor.h to accommodate the National PHY. The MAC
PHY combination will auto-negotiate at 100Mbps, Full duplex fine.
Furthermore, I seem to be able to read or write to the registers of
the PHY just fine. I have used the register dump routines to look at
the PHY registers. They reflect the values that I would expect. The
problem occurs when I try to TX or RX on packets. Every TX packet
reports an under run. However, when I look at the packet that plugs
is sending it is the correct length and has the correct content. The
other issue is that I have never been able to see a received packet.
I see the PHY TX and RX light blink but Ethereal connected to the
network shows no packets from the device. No debug information comes
up on the console port either. Has anyone on the list had these
problems? If so how did you solve it? Does anyone have any
suggestions? Any help would be appreciated.
Thanks in advance for any help,
Jeff Ballif
_______________________________________________
http://www.opencores.org/mailman/listinfo/ethmac
_______________________________________________
http://www.opencores.org/mailman/listinfo/ethmac
MaCo-Engineering
Dipl.-Ing. Marc Colling
Schlossstrasse 50
66352 Karlsbrunn
GERMANY
phone : (+49) 6809 / 7020190
fax : (+49) 6809 / 7020191
mobile : (+49) 170 / 7780788
Marc.Colling@MaCo-Engineering.de
www.MaCo-Engineering.de
_______________________________________________
http://www.opencores.org/mailman/listinfo/ethmac
|
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Underrun and RX issues
by Unknown on Aug 10, 2004 |
Not available! | ||
|
Sure Norm,
that's the problem you always will have if you need a constant minimum throuput on a shared memory bus. Also the MoreThanIP core can run into this problem if you can't guarantee enough bus bandwidth. So in my opinion it's not a problem of this core it's just a problem of creating a good design where this can't happen. E.g. simply enlarge the fifos in the opencores mac (file eth_defines.v; 4 defines must be changed). Regards, Marc At 15:52 09.08.2004 -0400, you wrote:
I understand the Opencores Emac Dma's data directly between memory and the
ethernet wire, with minimal (about 12 bytes, I believe) on chip buffering.
This amounts to "essentially" unbuffered transfers have to contend with
other concurrent NIOS bus and memory activities, such as instruction
fetches, memory accesses of the currently executing instruction, and any
other DMA operations (including a possible second simultaneous full duplex
Emac transfer). Excessive contention causes EMAC receive overruns and
transmit underruns.
The number of memory wait states almost certainly increases the risk of the
EMAC's DMA falling behind (we did conduct a few SDRAM versus SRAM tests, but
with inconclusive results).
Our experience has been that at least a 44 MHz core using the so called
"old" memory controller is required for reasonably adequate SDRAM operation
on a 100 mbit ethernet; with the so called "new" memory controller, it seems
that a 50 MHz core is too slow; 75 MHz appears adequate.
Our tests with cores running beneath the threshold clock frequency incurred
Rx overruns and Tx underruns; some of the DMA transfers that did not
over/under run were observed to corrupt the data being transferred.
Regards
Norm
-----Original Message-----
From: ethmac-bounces@opencores.org
[mailto:ethmac-bounces@opencores.org]On Behalf Of Marc Colling
Sent: Wednesday, August 04, 2004 11:18 AM
To: List about open source Ethernet MAC core
Subject: RE: [ethmac] Underrun and RX issues
Norm,
what kind of problems do you observed in 100Mbps with the OpenCores MAC?
Best Regards,
Marc
At 10:55 04.08.2004 -0400, you wrote:
MaCo-Engineering
Dipl.-Ing. Marc Colling
Schlossstrasse 50
66352 Karlsbrunn
GERMANY
phone : (+49) 6809 / 7020190
fax : (+49) 6809 / 7020191
mobile : (+49) 170 / 7780788
Marc.Colling@MaCo-Engineering.de
www.MaCo-Engineering.de
>Buy one of our uKit boards (see www.microtronix.com). While this ships with
>an MoreThanIp core, we could provide a NIOS II core supporting the OC EMAC.
>We have had good success with the EMAC but have observed problems Rx
>problems at slow 33/50MHz NIOS clock rates when connected to the ethernet
>MAC configured for 100Mbps. Try your board at 10Mbps, it should run fine.
>Our uKit board runs the NIOS II processor at over 110 MHz and supports the
>100Mbps EMAC just fine.
>
>-----Original Message-----
>From: ethmac-bounces@opencores.org
>[mailto:ethmac-bounces@opencores.org]On Behalf Of
>jballif@lonepeaklabs.com
>Sent: Thursday, July 22, 2004 2:06 PM
>To: ethmac@opencores.org
>Subject: [ethmac] Underrun and RX issues
>
>
>Folks,
>
>I have been working on a 10/100BaseT project using a National DP83847
> and a Altera Cyclone 1C12 running at 50Mhz using the Opencores MAC.
>I am using Altera's plugs library for the TCP stack. I have made the
>changes in igor.c and igor.h to accommodate the National PHY. The MAC
>PHY combination will auto-negotiate at 100Mbps, Full duplex fine.
>Furthermore, I seem to be able to read or write to the registers of
>the PHY just fine. I have used the register dump routines to look at
>the PHY registers. They reflect the values that I would expect. The
>problem occurs when I try to TX or RX on packets. Every TX packet
>reports an under run. However, when I look at the packet that plugs
>is sending it is the correct length and has the correct content. The
>other issue is that I have never been able to see a received packet.
>I see the PHY TX and RX light blink but Ethereal connected to the
>network shows no packets from the device. No debug information comes
>up on the console port either. Has anyone on the list had these
>problems? If so how did you solve it? Does anyone have any
>suggestions? Any help would be appreciated.
>
>Thanks in advance for any help,
>Jeff Ballif
>_______________________________________________
>http://www.opencores.org/mailman/listinfo/ethmac
>
>
>_______________________________________________
>http://www.opencores.org/mailman/listinfo/ethmac
MaCo-Engineering
Dipl.-Ing. Marc Colling
Schlossstrasse 50
66352 Karlsbrunn
GERMANY
phone : (+49) 6809 / 7020190
fax : (+49) 6809 / 7020191
mobile : (+49) 170 / 7780788
Marc.Colling@MaCo-Engineering.de
www.MaCo-Engineering.de
_______________________________________________
http://www.opencores.org/mailman/listinfo/ethmac
_______________________________________________
http://www.opencores.org/mailman/listinfo/ethmac
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