OpenCores
no use no use 1/1 no use no use
Connection between 1G eth UDP/IP Core and 10_100_1000 Mbps tri-mode ethernet MAC
by Micha87 on May 16, 2014
Micha87
Posts: 1
Joined: Apr 24, 2012
Last seen: May 26, 2014
Hello,
ist it possible to connect the opencores 1G eth UDP/IP Core
(http://opencores.org/project,udp_ip_stack)
and the opencores 10_100_1000 Mbps tri-mode ethernet MAC?
(http://opencores.org/project,ethernet_tri_mode)

If it is, is this correct?

UDP_Complete_nomac UDP_IP (
....
// MAC Transmitter
.mac_tx_tdata(tx_mac_data_int), //out
.mac_tx_tvalid(tx_mac_wr_int), //out
.mac_tx_tready(tx_mac_wa_int), //in
.mac_tx_tfirst(tx_mac_sop_int), //out
.mac_tx_tlast(tx_mac_eop_int), //out
// MAC Receiver
.mac_rx_tdata(rx_mac_data), //in
.mac_rx_tvalid(rx_mac_ra), //in
.mac_rx_tready(rx_mac_rd), //out
.mac_rx_tlast(rx_mac_eop) //in
);

And for what do I need the UDP/IP control signal. I cant find any hints in the documentation.

Thanks in advance
RE: Connection between 1G eth UDP/IP Core and 10_100_1000 Mbps tri-mode ethernet MAC
by indirasulo on May 18, 2014
indirasulo
Posts: 29
Joined: Jan 12, 2012
Last seen: Sep 26, 2014
Read the source code
type ip_control_type is record
arp_controls : arp_control_type;
end record;

type arp_control_type is
record
clear_cache : std_logic;
end record;

if control.clear_cache = '1' then
arp_entry.ip arp_entry.mac arp_entry.is_valid arp_entry.reply_required

it has only one signal that clears ARP cache (you probably want to hook this to reset)
RE: Connection between 1G eth UDP/IP Core and 10_100_1000 Mbps tri-mode ethernet MAC
by indirasulo on May 18, 2014
indirasulo
Posts: 29
Joined: Jan 12, 2012
Last seen: Sep 26, 2014
type ip_control_type is record
		arp_controls	: arp_control_type;
	end record;

type arp_control_type is
		record
				clear_cache	: std_logic;
		end record;

	if control.clear_cache = '1' then
					arp_entry.ip <= x"00000000";
					arp_entry.mac <= x"000000000000";
					arp_entry.is_valid <= '0';
					arp_entry.reply_required <= '0';
RE: Connection between 1G eth UDP/IP Core and 10_100_1000 Mbps tri-mode ethernet MAC
by h.domiry on Aug 12, 2014
h.domiry
Posts: 1
Joined: Apr 16, 2012
Last seen: Jan 2, 2019
MAC Transmitter in correct, but in MAC Receiver side, rx_mac_ra not mean valid.
This is "read able" and mean that MAC have a received data and could be read. it is like ready signal. In fact rx_mac_pa is valid signal for MAC IP core. correct port maping is like:

UDP_Complete_nomac UDP_IP (
....
// MAC Transmitter
.mac_tx_tdata(tx_mac_data_int), //out
.mac_tx_tvalid(tx_mac_wr_int), //out
.mac_tx_tready(tx_mac_wa_int), //in
.mac_tx_tfirst(tx_mac_sop_int), //out
.mac_tx_tlast(tx_mac_eop_int), //out
// MAC Receiver
.mac_rx_tdata(rx_mac_data), //in
.mac_rx_tvalid(rx_mac_pa), //in
.mac_rx_tready(rx_mac_ra), //out
.mac_rx_tlast(rx_mac_eop) //in
);
-- in VHDL
rx_mac_rd
RE: Connection between 1G eth UDP/IP Core and 10_100_1000 Mbps tri-mode ethernet MAC
by riscarc on Jan 20, 2015
riscarc
Posts: 1
Joined: Jun 12, 2008
Last seen: Sep 15, 2020
I guess there is something wrong with
.mac_rx_tready(rx_mac_ra), //out

isn't that supposed to be like :
.mac_rx_tready(rx_mac_rd), //out
RE: Connection between 1G eth UDP/IP Core and 10_100_1000 Mbps tri-mode ethernet MAC
by luigidp81 on May 18, 2015
luigidp81
Posts: 1
Joined: May 28, 2013
Last seen: Nov 29, 2016
Anyone has implemented these two cores on Altera Cyclone?
I've a problem in the connection between MAC and UDP. The FIFO has 32 bit data width and UDP only 8.

RE: Connection between 1G eth UDP/IP Core and 10_100_1000 Mbps tri-mode ethernet MAC
by cliffordjb on Nov 6, 2017
cliffordjb
Posts: 1
Joined: Jun 29, 2010
Last seen: Sep 16, 2018
using Xilinx ise core generator tool to build a fifo, the ports can be different widths, (i.e. 8 bit and 32 bit). altera tool should have similar flexibility, but I dunno for certain.
no use no use 1/1 no use no use
© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.