Hi,

Do anybody familiar with this core used wishbone master in burst mode? It run the testbench and encountered behaviour I do not exactly understand.

Please see the picture. It seems that during burst the first two chunk have the same DAT_O. On the other hand the fourth DAT_O (111213...) seems to be outside the cycle.

I can attach the other picture with some rx_fifo signals and it looks like it do not have enough time read read another value and thats why DAT_O is slipped one clock cycle.

Is it a correct behaviour?

It looks like I cannot attach pictures...

Yes, this would be much easier to look at with a waveform. Even if you can't post pictures, perhaps you could post a link. If not, maybe I can reproduce the issue. How are you running the tests (with FuseSoC, or manually?), which sim do you use and at what time do you see the issue

//Olof

Hi Olof,

Thank you for your reply. I sent you waveforms to your opencores mail. I'm not a wishbone specialist yet and maybe missed something. I used modelsim testbench scripts incorporated with the project. You will see the simulation time on the picture.

One more question. Are you familiar with this topic?
http://opencores.org/forum,Ethernet%20MAC,0,5201

The post is few years old but I'm, curious if the core has still any undocumented or unresolved bugs.

I hope I'm using the latest version. eth_wishbone file is revision 1.57.

kafka

Hi,

Just a heads up that I received the files, but haven't had time to look at them properly yet. I took a quick glance, and it does look weird. I wonder if it could be a delta cycle problem. I did also run the regression test suite successfully with icarus verilog using fusesoc (i.e fusesoc sim ethmac).

//Olof

Hi,

I simulated both in modelsim and ncsim. It looked like the testbench do not see this as a problem. I found this issue after integrating eth into my design and then confirmed with original testbench.

Incidentally, if you are looking for a 10/100 ethernet core that does pipelined wishbone interactions, you can find one as part of the OpenArty project. The core, though, is a slave peripheral to the bus, so it will take another device acting as a bus master (such as this DMA) to read any data into or out of it.
Dan

@Dan
Thank you. I will take a look on this project.

@Olof
Have you found a while to take a look into this issue?