Is it possible to use the ethmac core with the Nexys Video FPGA board ? It has a Realtek 8211E-VL PHY. As I understand it it's an RGMII interface but it seems to have almost the same signals as the ethmac core. Two signals I'm not sure about are rxctl and txctl.

Hi!

I have both an Arty board with an RMII interface, as well as a Nexys Video with an RGMII interface. The two are not compatible. The Nexys Video RGMII interface is *really* an 8-bit interface running at 125MHz, whereas the RMII interface is a four bit interface running at 25MHz.

I'm hoping to build an appropriate interface for my Nexys Video ... just haven't gotten to it yet. (Still working on copying video data to RAM, and reading it back from RAM ...)

Dan

Okay, I am confused by all the MII's. The Nexys Video physically has four bits input and output for Rxd, and Txd, and so does the PHY. The PHY passed back a 25 MHz clock, so it looks almost like an MII interface. On the spec sheet for the controller it mentions MII mode for 10/100 communications, and RGMII for 1Gb comm. However the PHY has two mysterious signals RxCtl and TxCtl. (It shows them also as RxDV and TxEn). But I think that's not enough signals for an MII interface. Some I'm wondering if some of the signals are multiplexed into the RxCtrl ? The Nexys4ddr has only two bits for Rxd and Txd and looks like an reduced interface. I built a MII to RGMII converter core in about a day for the Nexys4ddr. So I could use that core, but it doesn't look like an RGMII interface on the Nexys Video.

No, it's an RGMII interface all right. If you do a search on Digilent's forums over the last couple months, you'll even find a post where I admit being confused about this interface, and then figure out what's going on.

Try starting with the math: In order to support a 1Gbps bit rate, at 4-bits per second like the RMII interface uses, you need to transmit/receive at 250MHz. However, the PHY's interface only runs on a 125MHz clock. That means that the core must send values out the interface using a DDR mode--transmitting new values on both ends of the clock.

I started out looking at my own MII logic a while back, and then realized that I'd need to send 8'bits at a time through there in order to make timing. Hence, I figure I'm going to need to rebuild my own network core to make this work.

I think my MDIO controller will still work though.

Dan

For 1Gpbs comm. the controller is definitely RGMII according to the spec sheet. However it looks like it supports MII for 10/100 Mbps. There doesn't seems to be any docs on what the rxctl and txctl signals do for 10/100 Mbps rates. It looks to me like the rate is configurable in the BMCR register. I get the impression that selecting a lower rate uses the MII interface instead of RGMII. That would mean that a controller would have to support both. I am going to experiment.