Dear OC-H.264 team,
I would like to tell some words about the further development of video codecs. In my opinion, codecs base on stupid motion compensation and DCT (MPEG-4, h.263, h.264) have perfected and another breakthrough in the video compression is scarcely probable. Why take pains to work on something which has already been accomplished in both software and hardware?
I think it would be much more efficient and interesting to start elaborating new, free and intelligent codec.

The new trends in video is transition:
1. From YUV or YCbCr to the Bayer color mosaic, which we get from the sensor.
2. From DCT + antialiasing to the discrete wavelet transform (DWT), which works with the whole picture and is perfect to decorrelation color mosaic.
3. From searching motion vectors and splitting into macro blocks to the global motion compensation with further splitting the frame into background and moving objects.
4. From linear (like JPEG2000) to the nonlinear DWT coefficient quantization.
5. From patent not free arithmetic coder to the free range coder.

Today there are enough software research in all above fields to start hardware desing. In the nearest future we will complete 2D DWT module for FPGA Xilinx Spartan6 and Virtex6 and we will upload all information to your web-site.

Please, feel free to ask any questions.

Hi,
Your points seems fascinating. The focus of this project, however, is already set. I think your suggestions may provide a continuation project, or another project that may run in parallel to the current one.

In my own opinion, the open-hardware community is not yet experienced enough to start its own research-projects, or implement un-standardized cores (correct me if I'm wrong, but I understand that this is what you suggest).


The OC H.264 SoC project is meant for accomplishing "OPEN" hardware/software. This was never done before.

I'm happy you are about to contribute to the OC projects. I understand that you are skilled in the video-compression field. Your help with this project will be very appreciated.

Hi,
Now we plan to start new project : smart IP video camera for CCTV. We want to make two IP cam. The first is cheap sensor 2Mpix 30 fps, FPGA Spartan6, CPU i.MX27,
the second is expensive up to 4 sensors 2Mpix 30 fps or one 6.2 Mpix 60 fps(Sony IMX017CQE), FPGA Virtex6, CPU i.MX51. But it will be very good if we can change these
CPUs to OpenRISC-processor. It's my dream free software on free hardwere. We will need for our cameras :
1. DDR2 SDRAM controller
2. Ethernet 10/100 MII
3. USB 2 controller
4. Nand Flash controller
5. SD or Compact flash controller
Could you tell me is it really to gather all together from the free IP core? How much place does it take on FPGA?

From what I understand, the profiling and architecture definition will result in
a structured plan to implement critical blocks, one at a time, such as IDCT for example(among several really - refer to typical h.264 diagram via google),
that will be reusable anyway for any new kinds of transforms whether it's for video or
image applications.
ALso, just want to add that Virtex-6 and Spartan-6 have built-in(hard IP in the FPGA) DDR2 and DDR3 memory controllers which makes more room for codecs development