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RE: Verilog/VHDL by jamesedgar on Mar 20, 2011			jamesedgar Posts: 9 Joined: Sep 14, 2004 Last seen: Jun 26, 2020
Kaushik -- The project mentioned in my previous post was set up to be used in a real time video compression system. The code completes a log search of one macroblock every 512 clock cycles. With a clock speed of 54MHz, this can perform motion detection on an NTSC or PAL image with about 1mS of delay from the start of the second frame to the output of the fisrt motion vector for the top row of macroblocks. Multiple tests are being done at the same time comparing the current macroblock to the 9 macroblocks in the same and surrounding positions in the previous image. I assume you are using ARPS with an interest in skipping computations to save time whenever possible. This isn't really a concern with this code. However, if you are trying to find a better match, it might be possible to modify the search vectors based on predicted motion. The log search is done at 36 points, starting with 9 points 8 pixels apart, then 9 more 4 pixels around the best match, then 9 more 2 pixels around that match, and then 9 more surrounding that match. There is also a half pel check. You could certainly start the search somewhere other than the center of the macroblock if you have predicted motion vectors (assuming the search stays in the 48 x 48 pixel search area.) In this case, you might also want to skip the first set of searches that are 8 pixels apart. Several examples in the smaller test project actually don't find the optimum solution because there is a tie in the first log search, and the code takes the first point by default (this is mentioned in the test log.) If the start point was moved closer to the correct solution, the correct solution would probably be found. Adjusting the vertical coordinate would not be too difficult, since this value is used to determine which memory is read from local block ram. miny is the main variable, but there are several temporary copies that you would need to look at. Adjusting the horizontal value would be more difficult. Case statements are used based on the predictable values of minx. Once this was changed, these would all become arrays, and you would likely use even more resources than the project uses now (about half of a Xilinx Spartan 3 1600.) This wouldn't be a problem if your motion vector selected one of the earlier log points, and the tests were just continued from that point. James Kaushik -- The project mentioned in my previous post was set up to be used in a real time video compression system. The code completes a log search of one macroblock every 512 clock cycles. With a clock speed of 54MHz, this can perform motion detection on an NTSC or PAL image with about 1mS of delay from the start of the second frame to the output of the fisrt motion vector for the top row of macroblocks. Multiple tests are being done at the same time comparing the current macroblock to the 9 macroblocks in the same and surrounding positions in the previous image. I assume you are using ARPS with an interest in skipping computations to save time whenever possible. This isn't really a concern with this code. However, if you are trying to find a better match, it might be possible to modify the search vectors based on predicted motion. The log search is done at 36 points, starting with 9 points 8 pixels apart, then 9 more 4 pixels around the best match, then 9 more 2 pixels around that match, and then 9 more surrounding that match. There is also a half pel check. You could certainly start the search somewhere other than the center of the macroblock if you have predicted motion vectors (assuming the search stays in the 48 x 48 pixel search area.) In this case, you might also want to skip the first set of searches that are 8 pixels apart. Several examples in the smaller test project actually don't find the optimum solution because there is a tie in the first log search, and the code takes the first point by default (this is mentioned in the test log.) If the start point was moved closer to the correct solution, the correct solution would probably be found. Adjusting the vertical coordinate would not be too difficult, since this value is used to determine which memory is read from local block ram. miny is the main variable, but there are several temporary copies that you would need to look at. Adjusting the horizontal value would be more difficult. Case statements are used based on the predictable values of minx. Once this was changed, these would all become arrays, and you would likely use even more resources than the project uses now (about half of a Xilinx Spartan 3 1600.) This wouldn't be a problem if your motion vector selected one of the earlier log points, and the tests were just continued from that point. James

RE: Verilog/VHDL by gkamal on Mar 22, 2011			gkamal Posts: 3 Joined: Mar 14, 2011 Last seen: Apr 14, 2011
[q]gkamal I appreciate your interest. but VLSI is very vast. first be clear in which direction u r travelling to.[/q]kowshik.. thank u sir for u r response.in which direction means please can u explain more. now i am doing MTECH vlsi.. gkamal I appreciate your interest. but VLSI is very vast. first be clear in which direction u r travelling to. kowshik.. thank u sir for u r response.in which direction means please can u explain more. now i am doing MTECH vlsi..

RE: Verilog/VHDL by kaushik_mallibhat on Mar 22, 2011			kaushik_mallibhat Posts: 5 Joined: Feb 11, 2011 Last seen: Aug 10, 2011
tats great...! then u have options like going towards analog side if u r interested with. tats great...! then u have options like going towards analog side if u r interested with.

RE: Verilog/VHDL by gkamal on Mar 23, 2011			gkamal Posts: 3 Joined: Mar 14, 2011 Last seen: Apr 14, 2011
can u sugest me some basic books sir... to learn basic... can u sugest me some basic books sir... to learn basic...

RE: Verilog/VHDL by kaushik_mallibhat on Apr 18, 2011			kaushik_mallibhat Posts: 5 Joined: Feb 11, 2011 Last seen: Aug 10, 2011
hello james, i saw the code at this link...http://opencores.org/project,macroblock_motion_detection. can u suggest me how to implement using IP core memory.. hello james, i saw the code at this link...http://opencores.org/project,macroblock_motion_detection. can u suggest me how to implement using IP core memory..

RE: Verilog/VHDL by raveendras4a5 on May 3, 2011			raveendras4a5 Posts: 1 Joined: Nov 24, 2010 Last seen: Jan 29, 2013
hi, i am doing a projet named "HDB3 ENCODER". i need to design the circuit by verilog program. in that circuit i have D-flip flop block with set and reset inputs. can anyone tell the verilog code to design this block? please...... i am attaching the block figure.[q]<a href="uploads/1304409561_dff.jpg">dff.jpg</a> (5 kb)[/q] hi, i am doing a projet named "HDB3 ENCODER". i need to design the circuit by verilog program. in that circuit i have D-flip flop block with set and reset inputs. can anyone tell the verilog code to design this block? please...... i am attaching the block figure. dff.jpg (5 kb)

RE: Verilog/VHDL by alexx188 on Nov 22, 2011			alexx188 Posts: 1 Joined: May 14, 2011 Last seen: Apr 14, 2024
[q]Altera provides a free version of ModelSim which will simulate VHDL. I believe that Xilinx does the same. However, it is a windows only tool.[/q] Really? I am runing ModelSim Altera Starter Edition under native linux. Altera provides a free version of ModelSim which will simulate VHDL. I believe that Xilinx does the same. However, it is a windows only tool. Really? I am runing ModelSim Altera Starter Edition under native linux.

RE: Verilog/VHDL by rajuanand on Jul 3, 2014			rajuanand Posts: 1 Joined: Apr 20, 2014 Last seen: Jul 3, 2014
plz send me verilog code of motion compensation. plz send me verilog code of motion compensation.

RE: Verilog/VHDL by richard_vlamynck on Jul 30, 2014			richard_vlamynck Posts: 31 Joined: Sep 15, 2008 Last seen: Jan 24, 2016
[q]Altera provides a free version of ModelSim which will simulate VHDL. I believe that Xilinx does the same. However, it is a windows only tool.[/q] As of July 2014, Altera and Xilinx both supply a "free" version of Modelsim that will simulate either Verilog or VHDL. In both cases, it will run on either Windows or Linux, depending on which version (win/linux) of the "free" Altera or Xilinx tools you downloaded. If you have a Linux desktop and a Windows desktop, you could even install one copy on each, you would have to do two separate download/installs. The "free" version of Modelsim that comes with the Altera or Xilinx tools is limited to either Verilog or VHDL, you can only do one or the other, not both. Sidebar: If you pay for Modelsim, then you get a mixed language simulator that can do Verilog and VHDL in the same design/simulation. If you are a beginner, then pick one language or the other and stick with it for a while. Also, pick either Altera or Xilinx and stick with it for a while. You don't have to buy a board right away, you should learn how to use the all the simulation tools and create a testbench first. I hope this helps. Altera provides a free version of ModelSim which will simulate VHDL. I believe that Xilinx does the same. However, it is a windows only tool. As of July 2014, Altera and Xilinx both supply a "free" version of Modelsim that will simulate either Verilog or VHDL. In both cases, it will run on either Windows or Linux, depending on which version (win/linux) of the "free" Altera or Xilinx tools you downloaded. If you have a Linux desktop and a Windows desktop, you could even install one copy on each, you would have to do two separate download/installs. The "free" version of Modelsim that comes with the Altera or Xilinx tools is limited to either Verilog or VHDL, you can only do one or the other, not both. Sidebar: If you pay for Modelsim, then you get a mixed language simulator that can do Verilog and VHDL in the same design/simulation. If you are a beginner, then pick one language or the other and stick with it for a while. Also, pick either Altera or Xilinx and stick with it for a while. You don't have to buy a board right away, you should learn how to use the all the simulation tools and create a testbench first. I hope this helps.

RE: Verilog/VHDL by kavyaram on Dec 12, 2014			kavyaram Posts: 1 Joined: Sep 26, 2014 Last seen: Aug 12, 2019
Hello, I am doing my project on Enhanced LEON 3 processor.For this processor i'm going to write UPF.For that im using MAGELLAN(SYNOPSYS) tool. I just want to write the UPF only not from DESIGNING.so, please tell me where i can get the complete eLEON 3 processor code in verilog(completely executed) and also suggest me any other open source tools replacing with MVSIM,MVRC. Here is the design for the processor.Replay me as early as possible[q]<a href="uploads/1418375880_Formal Verification of Architectural Power Intent..pdf">Formal Verification of Architectural Power Intent..pdf</a> (1123 kb)[/q] Hello, I am doing my project on Enhanced LEON 3 processor.For this processor i'm going to write UPF.For that im using MAGELLAN(SYNOPSYS) tool. I just want to write the UPF only not from DESIGNING.so, please tell me where i can get the complete eLEON 3 processor code in verilog(completely executed) and also suggest me any other open source tools replacing with MVSIM,MVRC. Here is the design for the processor.Replay me as early as possible Formal Verification of Architectural Power Intent..pdf (1123 kb)

RE: Verilog/VHDL by baotri4893 on May 27, 2015			baotri4893 Posts: 1 Joined: May 14, 2015 Last seen: Jun 16, 2015
[q]Kaushik -- See: http://opencores.org/project,macroblock_motion_detection for verilog code to do motion estimation. There is a smaller project that uses a log search for the best match for a macroblock in a group of 9 macroblocks, and a more complicated project that uses the first project as a base and is timed to repeatedly do the same search on an entire video frame. James[/q] Hi James about your core i got problem when i try to build it."Node instance "searchram[0].mem" instantiates undefined entity "RAMB4_S16_S16"" and also currram.mem . could you explain it to me. my mail is: baotri4893@gmail.com. thank you very much. Kaushik -- See: http://opencores.org/project,macroblock_motion_detection for verilog code to do motion estimation. There is a smaller project that uses a log search for the best match for a macroblock in a group of 9 macroblocks, and a more complicated project that uses the first project as a base and is timed to repeatedly do the same search on an entire video frame. James Hi James about your core i got problem when i try to build it."Node instance "searchram[0].mem" instantiates undefined entity "RAMB4_S16_S16"" and also currram.mem . could you explain it to me. my mail is: baotri4893@gmail.com. thank you very much.

RE: Verilog/VHDL by jamesedgar on Jun 3, 2015			jamesedgar Posts: 9 Joined: Sep 14, 2004 Last seen: Jun 26, 2020
Attached is a simple replacement for the RAMB4_S16_S16 block. Note that resets and enables are ignored in this model. They were all tied off and unused in the referenced project. Using this file, the project builds in Vivado for an xc7k70tfbg676-1 and instantiates a RAMB18E1. I don't have a board, but the behavioral simulation looks good. James[q]<a href="uploads/1433319188_RAMB4_S16_S16_Replacement.v">RAMB4_S16_S16_Replacement.v</a> (1 kb)[/q] Attached is a simple replacement for the RAMB4_S16_S16 block. Note that resets and enables are ignored in this model. They were all tied off and unused in the referenced project. Using this file, the project builds in Vivado for an xc7k70tfbg676-1 and instantiates a RAMB18E1. I don't have a board, but the behavioral simulation looks good. James RAMB4_S16_S16_Replacement.v (1 kb)

NOC:Verilog/system c by kian_mary on Jul 28, 2015			kian_mary Posts: 9 Joined: Jul 27, 2015 Last seen: Nov 10, 2017
Hi I have to develop a NoC simulator in verilog or SystemC. First I must develop a simple NoC e.g. a 2x2 mesh, then add static VC organization (4 VC per channel), then expand the NoC to 4x4 or 8x8. anybody has the codes? and from where I can download these simulators? Hi I have to develop a NoC simulator in verilog or SystemC. First I must develop a simple NoC e.g. a 2x2 mesh, then add static VC organization (4 VC per channel), then expand the NoC to 4x4 or 8x8. anybody has the codes? and from where I can download these simulators?

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