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Testbench for image processing using Verilog HDL by maheshsubramanian on Jul 6, 2016			maheshsubramanian Posts: 1 Joined: Aug 31, 2015 Last seen: Jul 6, 2016
Hi, Anyone give some explanation(with example) about how to simulate image file through Verilog HDL test bench. In here I was attached test bench code for Stream scaler, Kindly give description about this code. I want to know how to assign image file in test bench through file declaration and also i want to know how to open .raw file or how to convert image file into raw file. Give the explanation about this file declaration: `define INPUT640x512 "src/input640x512RGB.raw" [q]<a href="uploads/1467788038_scaler_tb.v">scaler_tb.v</a> (6 kb)[/q] Hi, Anyone give some explanation(with example) about how to simulate image file through Verilog HDL test bench. In here I was attached test bench code for Stream scaler, Kindly give description about this code. I want to know how to assign image file in test bench through file declaration and also i want to know how to open .raw file or how to convert image file into raw file. Give the explanation about this file declaration: `define INPUT640x512 "src/input640x512RGB.raw" scaler_tb.v (6 kb)

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