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generating vcd file
by kian_mary on Oct 15, 2016
kian_mary
Posts: 9
Joined: Jul 27, 2015
Last seen: Nov 10, 2017
hello I am trying to generate a vcd file in verilog test fixture to get dynamic power value. I have implemented my design and then I have created a new source in verilog test fixture. I have added these code lines at the end of the test code(before endmodule): initial begin $dumpfile ("node_1_vcd.vcd"); $dumpvars(); in_flit_w = 18'b110001111000110100; ready_n = 1; #20 in_flit_w = 18'b010010111000110100; ready_n = 0; #1000 $dumpoff; end now when I want to simulate behavioral model this error appears: ERROR:Simulator:1026 - The switch -hwcosim_clock must be specified for hardware cosimulation. what sould I do? thank in advance
RE: generating vcd file
by dgisselq on Jun 30, 2017
dgisselq
Posts: 245
Joined: Feb 20, 2015
Last seen: Aug 18, 2019
Kian,

I'm not sure what simulator you are using, or why it's giving you the bug about a lack of a hardware cosimulation clock.

I do know that you can create a VCD file from a Verilator simulation using the techniques outlined here. I do it all the time. Feel free to check out my wbuart project for an example. There, you'll find Verilator simulations of hello world, a dump of the Gettysburg address over a simulated serial port, as well as a simple line testing program that waits for a line in only to repeat it back out.

Dan

P.S. I tend to get a security warning when creating an http: link to zipcpu.com. Just make sure you connect via http: (insecure) for now and that should dismiss the warning.

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