or1ksim: ETE bit in DMR1
by Unknown on Feb 6, 2004 |
Not available! | ||
For some reason when I look at the projects page, I don't see this project. I'm looking under uProcessors.
-Brian
-----Original Message-----
From: openrisc-bounces@opencores.org on behalf of Damjan Lampret
Sent: Wed 2/4/2004 3:42 AM
To: List about OpenRISC project
Cc:
Subject: Re: [openrisc] or1ksim: ETE bit in DMR1
http://www.opencores.org/projects/8051/
----- Original Message -----
From: "Brian Korsedal" BKorsedal@bms-inc.com>
To: "List about OpenRISC project" openrisc@opencores.org>; "List about
OpenRISC project" openrisc@opencores.org>
Sent: Thursday, February 05, 2004 12:24 AM
Subject: RE: [openrisc] or1ksim: ETE bit in DMR1
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
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Are their any open source 8051 cores? We have a programmer here who loves
the 8051, so if I can give him a soft 8051 @ 5 Mhz inside our FPGA, I think he would love it.
-----Original Message-----
From: openrisc-bounces@opencores.org on behalf of Bill Cox
Sent: Wed 2/4/2004 12:01 PM
To: List about OpenRISC project
Cc:
Subject: Re: [openrisc] or1ksim: ETE bit in DMR1
The 8051 choice seems natural.
Does anyone know if it's OK to clone PIC cores? I can't find anything
on the topic either way, but the MiniRISC core on OpenCores looks
promising for very small applications.
Bill
Damjan Lampret wrote:
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
>Go with 8051 or something like that. I think there is no legal issues
with
>8051.
>
>regards,
>Damjan
>
>----- Original Message -----
>From: "Brian Korsedal" BKorsedal@bms-inc.com>
>To: "List about OpenRISC project" openrisc@opencores.org>
>Sent: Wednesday, February 04, 2004 6:38 PM
>Subject: RE: [openrisc] or1ksim: ETE bit in DMR1
>
>
>
>
>
>_______________________________________________
>http://www.opencores.org/mailman/listinfo/openrisc
>
>
>
>We need a very simple 8-bit microcontroller inside an FPGA. I've found
>a few here on opencores, but I am not sure about their legality. Is
>there any way the or1k can be reduced to an 8-bit version or would it be
>easier to write an 8-bit microcontroller than used the or1k instruction
>set?
>
>We want a completely legal 8-bit soft core with a good C compiler. Any
>suggestions?
>
>-Brian
>
>-----Original Message-----
>From: openrisc-bounces@opencores.org
>[mailto:openrisc-bounces@opencores.org] On Behalf Of Damjan Lampret
>Sent: Tuesday, February 03, 2004 2:52 PM
>To: List about OpenRISC project
>Subject: Re: [openrisc] or1ksim: ETE bit in DMR1
>
>
>----- Original Message -----
>From: "Heiko Panther" heiko.panther@web.de>
>To: openrisc@opencores.org>
>Sent: Tuesday, February 03, 2004 6:07 PM
>Subject: Re: [openrisc] or1ksim: ETE bit in DMR1
>
>
>
>
>Also, the ETE bit could be ignored, and
> > >Wouldn't this cause some confusion when ETE is used and when not? > > >Well, looks to me as if the ETE bit is redundant. I noticed some more >redundancy; the DP bit in the DCR registers. What is it good for? > > >Isn't > >You mean the DVR/DCR (Register Pair) Present? > >This bit is there to tell the user (gdb, stub etc) how many DVR/DCRs are >there. Yes if you implement configuration registers then it is >redundant. > > >
>a single bit per watchpoint enough, enabling/disabling a trap
> > >exception? > >
>What other purposes are served by the second set of per-watchpoint
> > >bits, > >
>and by the all-encompassing ETE?
> >If the manual is being reworked, I suggest a little terminology > > >change. > >
>OR1K has these watchpoints that can be used to check various processor
>conditions. But the term "watchpoint" generally refers to checking the >effective data load/store address only, and the term "Breakpoint" to >checking the program counter only. >So I suggest calling these registers "Checkpoint registers" or in > > >short > >
>"Checkpoints". We should get rid of all occurences of "Breakpoint" and
>"Watchpoint" in the manual. Instead of saying "Watchpoints generating >Breakpoint" (as in DMR2[WPE] documentation) say "Checkpoints > > >generating > >
>Trap exception".
> > >Sounds good. > >Lets agree how to change the documentation. Do you wanna go and change >the >way you like it and then I'm gonna add my changes, do should I make al >lthe >changes and you review them (this second alternative might take more >time) > >regards, >Damjan > > >
>Heiko
>_______________________________________________
>http://www.opencores.org/mailman/listinfo/openrisc
>
>
>_______________________________________________
>http://www.opencores.org/mailman/listinfo/openrisc
>
>_______________________________________________
>http://www.opencores.org/mailman/listinfo/openrisc
>
>
|
or1ksim: ETE bit in DMR1
by Unknown on Feb 7, 2004 |
Not available! | ||
Because by default the project page will show only those projects marked as
Done. This project is not marked as Done.
regards,
Damjan
----- Original Message -----
From: "Brian Korsedal" BKorsedal@bms-inc.com>
To: "List about OpenRISC project" openrisc@opencores.org>
Sent: Friday, February 06, 2004 3:07 AM
Subject: RE: [openrisc] or1ksim: ETE bit in DMR1
For some reason when I look at the projects page, I don't see this project.
I'm looking under uProcessors.
-Brian
-----Original Message-----
From: openrisc-bounces@opencores.org on behalf of Damjan Lampret
Sent: Wed 2/4/2004 3:42 AM
To: List about OpenRISC project
Cc:
Subject: Re: [openrisc] or1ksim: ETE bit in DMR1
http://www.opencores.org/projects/8051/
----- Original Message -----
From: "Brian Korsedal" BKorsedal@bms-inc.com>
To: "List about OpenRISC project" openrisc@opencores.org>; "List about
OpenRISC project" openrisc@opencores.org>
Sent: Thursday, February 05, 2004 12:24 AM
Subject: RE: [openrisc] or1ksim: ETE bit in DMR1
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
----------------------------------------------------------------------------
----
Are their any open source 8051 cores? We have a programmer here who loves
the 8051, so if I can give him a soft 8051 @ 5 Mhz inside our FPGA, I think he would love it.
-----Original Message-----
From: openrisc-bounces@opencores.org on behalf of Bill Cox
Sent: Wed 2/4/2004 12:01 PM
To: List about OpenRISC project
Cc:
Subject: Re: [openrisc] or1ksim: ETE bit in DMR1
The 8051 choice seems natural.
Does anyone know if it's OK to clone PIC cores? I can't find anything
on the topic either way, but the MiniRISC core on OpenCores looks
promising for very small applications.
Bill
Damjan Lampret wrote:
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
>Go with 8051 or something like that. I think there is no legal issues
with
>8051.
>
>regards,
>Damjan
>
>----- Original Message -----
>From: "Brian Korsedal" BKorsedal@bms-inc.com>
>To: "List about OpenRISC project" openrisc@opencores.org>
>Sent: Wednesday, February 04, 2004 6:38 PM
>Subject: RE: [openrisc] or1ksim: ETE bit in DMR1
>
>
>
>
>
>_______________________________________________
>http://www.opencores.org/mailman/listinfo/openrisc
>
>
>
>We need a very simple 8-bit microcontroller inside an FPGA. I've found
>a few here on opencores, but I am not sure about their legality. Is
>there any way the or1k can be reduced to an 8-bit version or would it be
>easier to write an 8-bit microcontroller than used the or1k instruction
>set?
>
>We want a completely legal 8-bit soft core with a good C compiler. Any
>suggestions?
>
>-Brian
>
>-----Original Message-----
>From: openrisc-bounces@opencores.org
>[mailto:openrisc-bounces@opencores.org] On Behalf Of Damjan Lampret
>Sent: Tuesday, February 03, 2004 2:52 PM
>To: List about OpenRISC project
>Subject: Re: [openrisc] or1ksim: ETE bit in DMR1
>
>
>----- Original Message -----
>From: "Heiko Panther" heiko.panther@web.de>
>To: openrisc@opencores.org>
>Sent: Tuesday, February 03, 2004 6:07 PM
>Subject: Re: [openrisc] or1ksim: ETE bit in DMR1
>
>
>
>
>Also, the ETE bit could be ignored, and
> > >Wouldn't this cause some confusion when ETE is used and when not? > > >Well, looks to me as if the ETE bit is redundant. I noticed some more >redundancy; the DP bit in the DCR registers. What is it good for? > > >Isn't > >You mean the DVR/DCR (Register Pair) Present? > >This bit is there to tell the user (gdb, stub etc) how many DVR/DCRs are >there. Yes if you implement configuration registers then it is >redundant. > > >
>a single bit per watchpoint enough, enabling/disabling a trap
> > >exception? > >
>What other purposes are served by the second set of per-watchpoint
> > >bits, > >
>and by the all-encompassing ETE?
> >If the manual is being reworked, I suggest a little terminology > > >change. > >
>OR1K has these watchpoints that can be used to check various processor
>conditions. But the term "watchpoint" generally refers to checking the >effective data load/store address only, and the term "Breakpoint" to >checking the program counter only. >So I suggest calling these registers "Checkpoint registers" or in > > >short > >
>"Checkpoints". We should get rid of all occurences of "Breakpoint" and
>"Watchpoint" in the manual. Instead of saying "Watchpoints generating >Breakpoint" (as in DMR2[WPE] documentation) say "Checkpoints > > >generating > >
>Trap exception".
> > >Sounds good. > >Lets agree how to change the documentation. Do you wanna go and change >the >way you like it and then I'm gonna add my changes, do should I make al >lthe >changes and you review them (this second alternative might take more >time) > >regards, >Damjan > > >
>Heiko
>_______________________________________________
>http://www.opencores.org/mailman/listinfo/openrisc
>
>
>_______________________________________________
>http://www.opencores.org/mailman/listinfo/openrisc
>
>_______________________________________________
>http://www.opencores.org/mailman/listinfo/openrisc
>
>
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
|