Hi guys,

Not sure if you were able to resolve this or not but here's a list of the things I had to do to get minsoc working on the Digilent Atlys board:

1. Create a spartan6_atlys directory as described on the minsoc wiki.
2. In your new spartan6_atlys directory, make the following mods:
- Use xc6slx45-2-csg324 for your device part.
- Modify the ucf file you can download from Digilent using one of the other existing minsoc boards as a reference. Note that the Digilent ucf file uses gigabit GMII ethernet pin connections but minsoc requires 10/100 MII pin connections. The ethernet chip on the Atlys board supports the MII interface so you just need to check out the Atlys reference guide and ethernet chip data sheet to connect the right pins.
- In minsoc_defines.v, create a new device type (I called it SPARTAN6), use FPGA_CLOCK_DIVISION with a divisor of 2 and specify NEGATIVE_RESET.
3. Make the following modifications to or1200_defines.v:
- In the target FPGA memory section, define OR1200_XILINX_RAMB16.
- In the register file RAM section, define OR1200_RFRAM_DUALPORT (not OR1200_RFRAM_GENERIC).
4. In xilinx_dcm.v, you can allow the SPARTAN6 device to use the XILINX_DCM_SP define but you'll need to specify a value for CLKIN_PERIOD in the DCM_SP module (100 ns).
5. In xilinx_internal_jtag.v, create an instance of the BSCAN_SPARTAN6 module for the SPARTAN6 device.
6. In minsoc_onchip_ram.v, allow the SPARTAN6 device to use the MINSOC_XILINX_RAMB16 define.

With these modifications, adv_jtag_bridge can connect to the board using a xilinx USB jtag cable and the self test completes successfully. I can also upload software using or32-elf-gdb. I did all of this with the tools and minsoc code that was current as of December 2011.

Geoff

Hi guys,

Not sure if you were able to resolve this or not but here's a list of the things I had to do to get minsoc working on the Digilent Atlys board:

1. Create a spartan6_atlys directory as described on the minsoc wiki.
2. In your new spartan6_atlys directory, make the following mods:
- Use xc6slx45-2-csg324 for your device part.
- Modify the ucf file you can download from Digilent using one of the other existing minsoc boards as a reference. Note that the Digilent ucf file uses gigabit GMII ethernet pin connections but minsoc requires 10/100 MII pin connections. The ethernet chip on the Atlys board supports the MII interface so you just need to check out the Atlys reference guide and ethernet chip data sheet to connect the right pins.
- In minsoc_defines.v, create a new device type (I called it SPARTAN6), use FPGA_CLOCK_DIVISION with a divisor of 2 and specify NEGATIVE_RESET.
3. Make the following modifications to or1200_defines.v:
- In the target FPGA memory section, define OR1200_XILINX_RAMB16.
- In the register file RAM section, define OR1200_RFRAM_DUALPORT (not OR1200_RFRAM_GENERIC).
4. In xilinx_dcm.v, you can allow the SPARTAN6 device to use the XILINX_DCM_SP define but you'll need to specify a value for CLKIN_PERIOD in the DCM_SP module (100 ns).
5. In xilinx_internal_jtag.v, create an instance of the BSCAN_SPARTAN6 module for the SPARTAN6 device.
6. In minsoc_onchip_ram.v, allow the SPARTAN6 device to use the MINSOC_XILINX_RAMB16 define.

With these modifications, adv_jtag_bridge can connect to the board using a xilinx USB jtag cable and the self test completes successfully. I can also upload software using or32-elf-gdb. I did all of this with the tools and minsoc code that was current as of December 2011.

Geoff