Often the clock for the counters is much slower than the interface clock.  When this is true, it takes a while for the commands to ripple through, so that the counters can be read properly.  

Each gh_counter_control.vhd module has a rd_busy signal - when this signal is high, no ack will not go active - it was intended that this would create wait states until the command ripples through the counters.

When the counter uses the same clock as the interface clock (each counter has a boolean GENERIC which should be set to true when this is the case) this should be not be an issue.

A. LeFevre, Howard

a VHDL 8254 Timer

Hi Howard:

  I have a problem at readback command.

  When I set readback command and read only counter without status, like 0xD2.
  It will not response "ack".
  Is this a bug or you have a special consider??

Thanks,
Joe

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a VHDL 8254 Timer