a VHDL 8254 Timer

Hello,

1. Why there are two input lines: wb_stb_i, wb_cyc_i ? can I apply them both to CS from my address decoder?

2. I am following he waveform in the dpf file in order to work with Mode3 and try to read the data from the counters (direct read and even Readback) but don't get the valid data or the lines are constantly at 0. Can anyone post a full waveform to how do the above?

see my waveform here: http://yfrog.com/muwaveform8254j

Info: The input clock I used for the counters was 5 times slower (and in sync) than the system clock (wb_clk_i).

3. What is the maximum frequency for the clock inputs?

Many thanks in advance!

1. Those are both Wishbone defined signals - yes.

2. The design assumes that the two clocks are async, with no assumption about which one is a higher rate - to sync signals going between the two clocks a lot of register delays are used. Do you have the synchronous generics set to true? As long as the clocks are synchronous, that should minimize the data delay changing clock domains.