a VHDL 8254 Timer

Problem with updating value of the counter #4

Open pitterb opened this issue almost 11 years ago

I've got problem with updating value of the counter through APB interface, when updating two bytes (RW bits in control word set to "11"). Only LSB was updated. I've tried to find what's wrong and I made a change that helped (I don't know how this may affect other features). Here is output of diff command on gh_counter_control.vhd file:

    signal fe_hdcl   : std_logic;
    signal ird_busy  : std_logic;
    signal clr_hclsw : std_logic;

```
  signal iCSr      : std_logic;
```
begin
```
  process(clk_i, rst)
```
```
  begin
```
```
          if rst = '1' then
```
```
                  iCSr <= '0';
```
```
          elsif rising_edge(clk_i) then
```
```
                  iCSr <= iCS;
```
```
          end if;
```
```
  end process;
```

@@ -208,7 +218,7 @@ u2 : gh_register_ce '0';

    ld_msb <= '1' when ((dwr = '1') and (iA = "00") and (control(5 downto 4) = "10") and (iCS = '1')) else

            '1' when ((dwr = '1') and (iA = "00") and (control(5 downto 4) = "11") and (dwb = '1') and (iCS = '1')) else

            '1' when ((dwr = '1') and (iA = "00") and (control(5 downto 4) = "11") and (dwb = '1') and (iCSr = '1')) else
            '0';

  rd_lsb <= '0' when (hclsw = '1') else

Assignee

No one

Labels

Bug

Browse

a VHDL 8254 Timer