I have implemened a aes encryption code in vhdl and tested it on xilinx fpga spartan6. I have tested it on our various test vectors and it is working fine. But is there any official testing module or something which i can use to prove that my code is as per Fips specifications??
Kindly revert back at the earliest.
Hi
there is validation suite document by NIST that contains test vectors that covers statistically the AES algorithm you can find the link below
http://csrc.nist.gov/groups/STM/cavp/documents/aes/AESAVS.pdf
in this document you will find that the test vectors provided depends on mode of operation.read about modes of operation from the below link
http://en.wikipedia.org/wiki/Block_cipher_mode_of_operation
Thanks
Thanks:)
Hello
I am working in my final year project where I need to code AES algorithm on xilinx synthesizer. I am having difficulty in coding encryption and decryption modules. I would be glad if you can provide with the code in data flow modeling.
please kindly revert back as early as possible.