ao68000 - Wishbone 68000 core

I tested ao68000 in verilog simulator. I tried 68000 monotr program,but dose not work.

I think DBRA(DBcc) have a problem.

68k montor source :

lea	traperr(pc),a0
lea	$80,a1
moveq	#15,d0

trapset move.l a0,(a1)+ dbra d0,trapset

simulation d0 value : $0000000f $0000000e . . $00000000 $0000ffff <- dbra loop not end !! $0000fffe <- ????

Thank you

Thank you for your bug report.

You are correct - there was a bug in the DBcc opcode microcode. I have commited a fix to the microcode.

If you are willing to check the fix, please do - and send a reply comment :)

Once more, thank you. Aleksander Osman.

Thank you for update! 'DBRA' code is ok. I continue simulation it.