There's a typo common to the headers of all verilog source files in this project:
cpu.v:// the OpenIP Licensed core as a building black without datapath.v:// the OpenIP Licensed core as a building black without decode.v:// the OpenIP Licensed core as a building black without defines.v:// the OpenIP Licensed core as a building black without lib_fpga.v:// the OpenIP Licensed core as a building black without lib.v:// the OpenIP Licensed core as a building black without memory_fpga.v:// the OpenIP Licensed core as a building black without memory.v:// the OpenIP Licensed core as a building black without mem.v:// the OpenIP Licensed core as a building black without mult.v:// the OpenIP Licensed core as a building black without pio.v:// the OpenIP Licensed core as a building black without register.v:// the OpenIP Licensed core as a building black without sys.v:// the OpenIP Licensed core as a building black without test.v:// the OpenIP Licensed core as a building black without timescale.v:// the OpenIP Licensed core as a building black without top.v:// the OpenIP Licensed core as a building black without uart.v:// the OpenIP Licensed core as a building black without
looks like a copy'n'paste bug. (sorry for being pedantic)