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Pipe Balancing #1
Open ghannoum opened this issue almost 13 years ago
ghannoum commented almost 13 years ago

Hello, Correct me if I am wrong, but by looking at the code of the entity colorconv, it seems there is a bug at the rounding stage: y1r <= y1sh+y1w(f_factors_part-1); The fractional bit that is being added to the result was not delayed appropriately in order to balance the pipeline. I would suggest the fix to be as such: y1w_1d <= y1w(f_factors_part-1); y1w_2d <= y1w_1d; y1r <= y1sh+y1w_2d;

Also the same applies to the outputs y1c and y1. y1 has an extra delay latency over y1c, but both signals are sharing the same DOUT_RDY signal. A fix would be something like: --(in the clocked process) y1r_1d <= y1r; --(in the architecture) y1c <= y1r_1d(data_width+int_factors_part-1 downto data_width);

Anthony.


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