Data Flow Processor

code in verilog

There are plans to put DFP (more recently, GCA) into Verilog, but first I must learn Verilog. No committed dates as of yet. However since all the code is posted, it is possible that someone with Verilog experience could beat me to it. Also there are some VHDL to Verilog translators out there that could be tried. Since most hw tools compile both languages, it is possible to mix IPs from different languages as my colleague is doing.

Rob